[J-u-boot.git] / include / configs / hmi1001.h

/*
 * (C) Copyright 2003-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+ 
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU		*/
#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU)	*/
#define CONFIG_HMI1001		1	/* HMI1001 board			*/

#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE	0xFFF00000
#endif

#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz		*/

#define CONFIG_BOARD_EARLY_INIT_R

#define CONFIG_HIGH_BATS	1	/* High BATs supported			*/

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1	*/
#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps	*/
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/* Partitions */
#define CONFIG_DOS_PARTITION


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DATE
#define CONFIG_CMD_DISPLAY
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_IDE
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SNTP


#define	CONFIG_TIMESTAMP	1	/* Print image info with timestamp */

#if (CONFIG_SYS_TEXT_BASE == 0xFFF00000) /* Boot low */
#   define CONFIG_SYS_LOWBOOT		1
#endif

/*
 * Autobooting
 */
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */

#define CONFIG_PREBOOT	"echo;" \
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"flash_nfs=run nfsargs addip;"					\
		"bootm ${kernel_addr}\0"				\
	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"	\
	"rootpath=/opt/eldk/ppc_82xx\0"					\
	""

#define CONFIG_BOOTCOMMAND	"run net_nfs"

#define CONFIG_MISC_INIT_R	1

/*
 * IPB Bus clocking configuration.
 */
#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #1 or #2 */

#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE		0x7F

/*
 * EEPROM configuration
 */
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x58
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10

/*
 * RTC configuration
 */
#define CONFIG_RTC_PCF8563
#define CONFIG_SYS_I2C_RTC_ADDR		0x51

/*
 * Flash configuration
 */
#define CONFIG_SYS_FLASH_BASE		0xFF800000

#define CONFIG_SYS_FLASH_SIZE		0x00800000 /* 8 MByte */
#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max num of sects on one chip */

#define CONFIG_ENV_ADDR		(CONFIG_SYS_TEXT_BASE+0x40000) /* second sector */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks
					   (= chip selects) */
#define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (in ms)	*/

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_CFI_AMD_RESET

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_SIZE		0x4000
#define CONFIG_ENV_SECT_SIZE	0x20000
#define CONFIG_ENV_OFFSET_REDUND   (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND     (CONFIG_ENV_SIZE)

/*
 * Memory map
 */
#define CONFIG_SYS_MBAR		0xF0000000
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
#define CONFIG_SYS_DISPLAY_BASE	0x80600000
#define CONFIG_SYS_STATUS1_BASE	0x80600200
#define CONFIG_SYS_STATUS2_BASE	0x80600300

/* Settings for XLB = 132 MHz */
#define SDRAM_DDR	 1
#define SDRAM_MODE      0x018D0000
#define SDRAM_EMODE     0x40090000
#define SDRAM_CONTROL   0x714f0f00
#define SDRAM_CONFIG1   0x73722930
#define SDRAM_CONFIG2   0x47770000
#define SDRAM_TAPDELAY  0x10000000

/* Use ON-Chip SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM

/* preserve space for the post_word at end of on-chip SRAM */
#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)

#ifdef CONFIG_POST
#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_POST_SIZE
#else
#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
#endif

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#   define CONFIG_SYS_RAMBOOT		1
#endif

#define CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
#define CONFIG_SYS_MALLOC_LEN		(512 << 10)	/* Reserve 128 kB for malloc()	*/
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
#define CONFIG_MPC5xxx_FEC_MII100
#define CONFIG_PHY_ADDR		0x00
#define CONFIG_MII		1		/* MII PHY management		*/

/*
 * GPIO configuration
 */
#define CONFIG_SYS_GPS_PORT_CONFIG	0x01051004

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	    */
#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt   */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size  */
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size  */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

/* Enable an alternate, more extensive memory test */
#define CONFIG_SYS_ALT_MEMTEST

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */

#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */

/*
 * Enable loopw command.
 */
#define CONFIG_LOOPW

/*
 * Various low-level settings
 */
#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL		HID0_ICE

#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_CFG		0x0004FB00
#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE

/* 8Mbit SRAM @0x80100000 */
#define CONFIG_SYS_CS1_START		0x80100000
#define CONFIG_SYS_CS1_SIZE		0x00100000
#define CONFIG_SYS_CS1_CFG		0x19B00

/* FRAM 32Kbyte @0x80700000 */
#define CONFIG_SYS_CS2_START		0x80700000
#define CONFIG_SYS_CS2_SIZE		0x00008000
#define CONFIG_SYS_CS2_CFG		0x19800

/* Display H1, Status Inputs, EPLD @0x80600000 */
#define CONFIG_SYS_CS3_START		0x80600000
#define CONFIG_SYS_CS3_SIZE		0x00100000
#define CONFIG_SYS_CS3_CFG		0x00019800

#define CONFIG_SYS_CS_BURST		0x00000000
#define CONFIG_SYS_CS_DEADCYCLE	0x33333333

/*-----------------------------------------------------------------------
 * IDE/ATA stuff Supports IDE harddisk
 *-----------------------------------------------------------------------
 */

#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/

#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/

#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 2 drives per IDE bus	*/

#define CONFIG_IDE_PREINIT	1

#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA

/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)

/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)

/* Offset for alternate registers	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)

/* Interval between registers                                                */
#define CONFIG_SYS_ATA_STRIDE          4

#define CONFIG_ATAPI            1

#define CONFIG_VIDEO_SMI_LYNXEM
#define CONFIG_CFB_CONSOLE
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_LOGO

/*
 * PCI Mapping:
 * 0x40000000 - 0x4fffffff - PCI Memory
 * 0x50000000 - 0x50ffffff - PCI IO Space
 */
#define CONFIG_PCI		1
#define CONFIG_PCI_PNP		1
#define CONFIG_PCI_SCAN_SHOW	1
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1

#define CONFIG_PCI_MEM_BUS	0x40000000
#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE	0x10000000

#define CONFIG_PCI_IO_BUS	0x50000000
#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE	0x01000000

#define CONFIG_SYS_ISA_IO		CONFIG_PCI_IO_BUS

/*---------------------------------------------------------------------*/
/* Display addresses						       */
/*---------------------------------------------------------------------*/

#define CONFIG_PDSP188x
#define CONFIG_SYS_DISP_CHR_RAM	(CONFIG_SYS_DISPLAY_BASE + 0x38)
#define CONFIG_SYS_DISP_CWORD		(CONFIG_SYS_DISPLAY_BASE + 0x30)

#endif /* __CONFIG_H */
Commit	Line	Data
a87589da WD	1	/*
	2	* (C) Copyright 2003-2005
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
a87589da WD	6	*/
	7
	8	#ifndef __CONFIG_H
	9	#define __CONFIG_H
	10
	11	/*
	12	* High Level Configuration Options
	13	* (easy to change)
	14	*/
	15
	16	#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
	17	#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
	18	#define CONFIG_HMI1001 1 /* HMI1001 board */
	19
2ae18241 WD	20	#ifndef CONFIG_SYS_TEXT_BASE
	21	#define CONFIG_SYS_TEXT_BASE 0xFFF00000
	22	#endif
	23
6d0f6bcf	24	#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
a87589da	25
a87589da WD	26	#define CONFIG_BOARD_EARLY_INIT_R
a87589da WD	27
31d82672 BB	28	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31d82672 BB	29
a87589da WD	30	/*
	31	* Serial console configuration
	32	*/
	33	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	34	#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
6d0f6bcf	35	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
a87589da	36
08abe158 WD	37	/* Partitions */
	38	#define CONFIG_DOS_PARTITION
	39
48d5d102	40
7f5c0157 JL	41	/*
	42	* BOOTP options
	43	*/
	44	#define CONFIG_BOOTP_BOOTFILESIZE
	45	#define CONFIG_BOOTP_BOOTPATH
	46	#define CONFIG_BOOTP_GATEWAY
	47	#define CONFIG_BOOTP_HOSTNAME
	48
	49
a87589da	50	/*
48d5d102	51	* Command line configuration.
a87589da	52	*/
48d5d102 JL	53	#include <config_cmd_default.h>
	54
	55	#define CONFIG_CMD_DATE
	56	#define CONFIG_CMD_DISPLAY
	57	#define CONFIG_CMD_DHCP
	58	#define CONFIG_CMD_EEPROM
	59	#define CONFIG_CMD_I2C
	60	#define CONFIG_CMD_IDE
	61	#define CONFIG_CMD_NFS
	62	#define CONFIG_CMD_PCI
	63	#define CONFIG_CMD_SNTP
	64
a87589da WD	65
	66	#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
	67
14d0a02a	68	#if (CONFIG_SYS_TEXT_BASE == 0xFFF00000) /* Boot low */
6d0f6bcf	69	# define CONFIG_SYS_LOWBOOT 1
a87589da WD	70	#endif
	71
	72	/*
	73	* Autobooting
	74	*/
	75	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	76
	77	#define CONFIG_PREBOOT "echo;" \
32bf3d14	78	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
a87589da WD	79	"echo"
	80
	81	#undef CONFIG_BOOTARGS
	82
	83	#define CONFIG_EXTRA_ENV_SETTINGS \
	84	"netdev=eth0\0" \
	85	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b	86	"nfsroot=${serverip}:${rootpath}\0" \
a87589da	87	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b WD	88	"addip=setenv bootargs ${bootargs} " \
	89	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	90	":${hostname}:${netdev}:off panic=1\0" \
a87589da	91	"flash_nfs=run nfsargs addip;" \
fe126d8b WD	92	"bootm ${kernel_addr}\0" \
fe126d8b WD	93	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
a87589da WD	94	"rootpath=/opt/eldk/ppc_82xx\0" \
	95	""
	96
	97	#define CONFIG_BOOTCOMMAND "run net_nfs"
	98
9f96ae44 WD	99	#define CONFIG_MISC_INIT_R 1
9f96ae44 WD	100
a87589da WD	101	/*
	102	* IPB Bus clocking configuration.
	103	*/
6d0f6bcf	104	#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
a87589da	105
342717f7 WD	106	/*
	107	* I2C configuration
	108	*/
	109	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
6d0f6bcf	110	#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
342717f7	111
6d0f6bcf JCPV	112	#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
6d0f6bcf JCPV	113	#define CONFIG_SYS_I2C_SLAVE 0x7F
342717f7 WD	114
	115	/*
	116	* EEPROM configuration
	117	*/
6d0f6bcf JCPV	118	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58
	119	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	120	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
	121	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
342717f7 WD	122
	123	/*
	124	* RTC configuration
	125	*/
	126	#define CONFIG_RTC_PCF8563
6d0f6bcf	127	#define CONFIG_SYS_I2C_RTC_ADDR 0x51
342717f7	128
a87589da WD	129	/*
	130	* Flash configuration
	131	*/
6d0f6bcf	132	#define CONFIG_SYS_FLASH_BASE 0xFF800000
a87589da	133
6d0f6bcf JCPV	134	#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */
6d0f6bcf JCPV	135	#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max num of sects on one chip */
a87589da	136
14d0a02a	137	#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE+0x40000) /* second sector */
6d0f6bcf	138	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
a87589da	139	(= chip selects) */
6d0f6bcf JCPV	140	#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
6d0f6bcf JCPV	141	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
a87589da	142
00b1883a	143	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	144	#define CONFIG_SYS_FLASH_CFI
	145	#define CONFIG_SYS_FLASH_EMPTY_INFO
	146	#define CONFIG_SYS_FLASH_CFI_AMD_RESET
a87589da WD	147
	148	/*
	149	* Environment settings
	150	*/
5a1aceb0	151	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	152	#define CONFIG_ENV_SIZE 0x4000
	153	#define CONFIG_ENV_SECT_SIZE 0x20000
	154	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
	155	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
a87589da WD	156
	157	/*
	158	* Memory map
	159	*/
6d0f6bcf JCPV	160	#define CONFIG_SYS_MBAR 0xF0000000
	161	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	162	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
	163	#define CONFIG_SYS_DISPLAY_BASE 0x80600000
	164	#define CONFIG_SYS_STATUS1_BASE 0x80600200
	165	#define CONFIG_SYS_STATUS2_BASE 0x80600300
a87589da WD	166
	167	/* Settings for XLB = 132 MHz */
	168	#define SDRAM_DDR 1
	169	#define SDRAM_MODE 0x018D0000
	170	#define SDRAM_EMODE 0x40090000
	171	#define SDRAM_CONTROL 0x714f0f00
	172	#define SDRAM_CONFIG1 0x73722930
	173	#define SDRAM_CONFIG2 0x47770000
	174	#define SDRAM_TAPDELAY 0x10000000
	175
	176	/* Use ON-Chip SRAM until RAM will be available */
6d0f6bcf	177	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
800eb096	178
a87589da	179	/* preserve space for the post_word at end of on-chip SRAM */
800eb096 MZ	180	#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
	181
	182	#ifdef CONFIG_POST
553f0982	183	#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
a87589da	184	#else
553f0982	185	#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
a87589da WD	186	#endif
a87589da WD	187
25ddd1fb	188	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	189	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
a87589da	190
14d0a02a	191	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	192	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	193	# define CONFIG_SYS_RAMBOOT 1
a87589da WD	194	#endif
a87589da WD	195
6d0f6bcf JCPV	196	#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
	197	#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 128 kB for malloc() */
	198	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
a87589da WD	199
	200	/*
	201	* Ethernet configuration
	202	*/
	203	#define CONFIG_MPC5xxx_FEC 1
86321fc1	204	#define CONFIG_MPC5xxx_FEC_MII100
a87589da	205	#define CONFIG_PHY_ADDR 0x00
8d7e2732	206	#define CONFIG_MII 1 /* MII PHY management */
a87589da WD	207
	208	/*
	209	* GPIO configuration
	210	*/
6d0f6bcf	211	#define CONFIG_SYS_GPS_PORT_CONFIG 0x01051004
a87589da	212
a87589da WD	213	/*
	214	* Miscellaneous configurable options
	215	*/
6d0f6bcf JCPV	216	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	217	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
48d5d102	218	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	219	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
a87589da	220	#else
6d0f6bcf	221	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
a87589da	222	#endif
6d0f6bcf JCPV	223	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	224	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	225	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
a87589da	226
6d0f6bcf	227	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
48d5d102	228	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	229	# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
48d5d102 JL	230	#endif
48d5d102 JL	231
a87589da	232	/* Enable an alternate, more extensive memory test */
6d0f6bcf	233	#define CONFIG_SYS_ALT_MEMTEST
a87589da	234
6d0f6bcf JCPV	235	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	236	#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
a87589da	237
6d0f6bcf	238	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
a87589da	239
6d0f6bcf	240	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
a87589da WD	241
a87589da WD	242	/*
7f5c0157	243	* Enable loopw command.
a87589da WD	244	*/
	245	#define CONFIG_LOOPW
	246
	247	/*
	248	* Various low-level settings
	249	*/
6d0f6bcf JCPV	250	#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
6d0f6bcf JCPV	251	#define CONFIG_SYS_HID0_FINAL HID0_ICE
a87589da	252
6d0f6bcf JCPV	253	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	254	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	255	#define CONFIG_SYS_BOOTCS_CFG 0x0004FB00
	256	#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
	257	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
a87589da WD	258
a87589da WD	259	/* 8Mbit SRAM @0x80100000 */
6d0f6bcf JCPV	260	#define CONFIG_SYS_CS1_START 0x80100000
	261	#define CONFIG_SYS_CS1_SIZE 0x00100000
	262	#define CONFIG_SYS_CS1_CFG 0x19B00
a87589da WD	263
a87589da WD	264	/* FRAM 32Kbyte @0x80700000 */
6d0f6bcf JCPV	265	#define CONFIG_SYS_CS2_START 0x80700000
	266	#define CONFIG_SYS_CS2_SIZE 0x00008000
	267	#define CONFIG_SYS_CS2_CFG 0x19800
a87589da WD	268
a87589da WD	269	/* Display H1, Status Inputs, EPLD @0x80600000 */
6d0f6bcf JCPV	270	#define CONFIG_SYS_CS3_START 0x80600000
	271	#define CONFIG_SYS_CS3_SIZE 0x00100000
	272	#define CONFIG_SYS_CS3_CFG 0x00019800
a87589da	273
6d0f6bcf JCPV	274	#define CONFIG_SYS_CS_BURST 0x00000000
6d0f6bcf JCPV	275	#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
a87589da	276
08abe158 WD	277	/*-----------------------------------------------------------------------
	278	* IDE/ATA stuff Supports IDE harddisk
	279	*-----------------------------------------------------------------------
	280	*/
	281
	282	#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
	283
	284	#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
	285	#undef CONFIG_IDE_LED /* LED for ide not supported */
	286
6d0f6bcf JCPV	287	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
6d0f6bcf JCPV	288	#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
08abe158	289
9d3338d2 WD	290	#define CONFIG_IDE_PREINIT 1
9d3338d2 WD	291
6d0f6bcf	292	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
08abe158	293
6d0f6bcf	294	#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
08abe158 WD	295
08abe158 WD	296	/* Offset for data I/O */
6d0f6bcf	297	#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
08abe158 WD	298
08abe158 WD	299	/* Offset for normal register accesses */
6d0f6bcf	300	#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
08abe158 WD	301
08abe158 WD	302	/* Offset for alternate registers */
6d0f6bcf	303	#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
08abe158 WD	304
08abe158 WD	305	/* Interval between registers */
6d0f6bcf	306	#define CONFIG_SYS_ATA_STRIDE 4
08abe158 WD	307
	308	#define CONFIG_ATAPI 1
	309
ccd9d3d6 WD	310	#define CONFIG_VIDEO_SMI_LYNXEM
	311	#define CONFIG_CFB_CONSOLE
	312	#define CONFIG_VGA_AS_SINGLE_DEVICE
	313	#define CONFIG_VIDEO_LOGO
	314
98128f38 WD	315	/*
	316	* PCI Mapping:
	317	* 0x40000000 - 0x4fffffff - PCI Memory
	318	* 0x50000000 - 0x50ffffff - PCI IO Space
	319	*/
	320	#define CONFIG_PCI 1
	321	#define CONFIG_PCI_PNP 1
	322	#define CONFIG_PCI_SCAN_SHOW 1
f33fca22	323	#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
98128f38 WD	324
	325	#define CONFIG_PCI_MEM_BUS 0x40000000
	326	#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
	327	#define CONFIG_PCI_MEM_SIZE 0x10000000
	328
	329	#define CONFIG_PCI_IO_BUS 0x50000000
	330	#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
	331	#define CONFIG_PCI_IO_SIZE 0x01000000
	332
6d0f6bcf	333	#define CONFIG_SYS_ISA_IO CONFIG_PCI_IO_BUS
ccd9d3d6	334
9f96ae44 WD	335	/---------------------------------------------------------------------/
	336	/* Display addresses */
	337	/---------------------------------------------------------------------/
	338
7f0d241d	339	#define CONFIG_PDSP188x
6d0f6bcf JCPV	340	#define CONFIG_SYS_DISP_CHR_RAM (CONFIG_SYS_DISPLAY_BASE + 0x38)
6d0f6bcf JCPV	341	#define CONFIG_SYS_DISP_CWORD (CONFIG_SYS_DISPLAY_BASE + 0x30)
9f96ae44	342
a87589da	343	#endif /* __CONFIG_H */