[J-u-boot.git] / include / configs / TOP860.h

/*
 * (C) Copyright 2003
 * EMK Elektronik GmbH <www.emk-elektronik.de>
 * Reinhard Meyer <r.meyer@emk-elektronik.de>
 *
 * Configuation settings for the TOP860 board.
 *
 * -----------------------------------------------------------------
 * SPDX-License-Identifier:	GPL-2.0+
 */
/*
 * TOP860 is a simple module:
 * 16-bit wide FLASH on CS0	(2MB or more)
 * 32-bit wide DRAM on CS2 (either 4MB or 16MB)
 * FEC with Am79C874 100-Base-T and Fiber Optic
 * Ports available, but we choose SMC1 for Console
 * 8k I2C EEPROM at address 0xae, 6k user available, 2k factory set
 * 32768Hz crystal PLL set for 49.152MHz Core and 24.576MHz Bus Clock
 *
 * This config has been copied from MBX.h / MBX860T.h
 */
/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

/*-----------------------------------------------------------------------
 * CPU and BOARD type
 */
#define CONFIG_MPC860	1	/* This is a MPC860 CPU		*/
#define CONFIG_MPC860T	1	/* even better... an FEC!	*/
#define CONFIG_TOP860	1	/* ...on a TOP860 module	*/

#define	CONFIG_SYS_TEXT_BASE	0x80000000

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
#define	CONFIG_IDENT_STRING " EMK TOP860"

/*-----------------------------------------------------------------------
 * CLOCK settings
 */
#define	CONFIG_SYSCLK	49152000
#define	CONFIG_SYS_XTAL		32768
#define	CONFIG_EBDF		1
#define	CONFIG_COM		3
#define	CONFIG_RTC_MPC8xx

/*-----------------------------------------------------------------------
 * Physical memory map as defined by EMK
 */
#define CONFIG_SYS_IMMR		0xFFF00000	/* Internal Memory Mapped Register */
#define	CONFIG_SYS_FLASH_BASE	0x80000000	/* FLASH in final mapping */
#define	CONFIG_SYS_DRAM_BASE	0x00000000	/* DRAM in final mapping */
#define	CONFIG_SYS_FLASH_MAX	0x00400000	/* max FLASH to expect */
#define	CONFIG_SYS_DRAM_MAX	0x01000000	/* max DRAM to expect */

/*-----------------------------------------------------------------------
 * derived values
 */
#define	CONFIG_SYS_MF			(CONFIG_SYSCLK/CONFIG_SYS_XTAL)
#define	CONFIG_SYS_CPUCLOCK	CONFIG_SYSCLK
#define	CONFIG_SYS_BRGCLOCK	CONFIG_SYSCLK
#define	CONFIG_SYS_BUSCLOCK	(CONFIG_SYSCLK >> CONFIG_EBDF)
#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
#define	CONFIG_8xx_GCLK_FREQ	CONFIG_SYSCLK

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define	CONFIG_SYS_FLASH_CFI

/*-----------------------------------------------------------------------
 * Command interpreter
 */
#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#undef	CONFIG_8xx_CONS_SMC2
#define CONFIG_BAUDRATE		9600

/*
 * Allow partial commands to be matched to uniqueness.
 */
#define CONFIG_SYS_MATCH_PARTIAL_CMD


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_DATE
#define CONFIG_CMD_MII
#define CONFIG_CMD_BEDBUG


#define	CONFIG_SOURCE			1
#define	CONFIG_SYS_LOADS_BAUD_CHANGE	1
#undef	CONFIG_LOADS_ECHO			/* NO echo on for serial download	*/


#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/

#undef	CONFIG_SYS_HUSH_PARSER			/* Hush parse for U-Boot	*/


#if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
 #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif

#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

/*-----------------------------------------------------------------------
 * Memory Test Command
 */
#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

/*-----------------------------------------------------------------------
 * Environment handler
 * only the first 6k in EEPROM are available for user. Of that we use 256b
 */
#define CONFIG_ENV_IS_IN_EEPROM	1	/* turn on EEPROM env feature */
#define CONFIG_ENV_OFFSET		0x1000
#define CONFIG_ENV_SIZE		0x0700
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
#define CONFIG_SYS_FACT_OFFSET		0x1800
#define CONFIG_SYS_FACT_SIZE		0x0800
#define CONFIG_SYS_I2C_FACT_ADDR	0x57
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_EEPROM_SIZE 0x2000
#define	CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12
#define CONFIG_ENV_OVERWRITE
#define CONFIG_MISC_INIT_R

#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
#define CONFIG_SYS_I2C_SOFT_SPEED	100000
#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
/**/
#define	SDA	0x00010
#define	SCL	0x00020
#define __I2C_DIR	immr->im_cpm.cp_pbdir
#define __I2C_DAT	immr->im_cpm.cp_pbdat
#define __I2C_PAR	immr->im_cpm.cp_pbpar
#define	__I2C_ODR	immr->im_cpm.cp_pbodr
#define	I2C_INIT	{ __I2C_PAR &= ~(SDA|SCL);	\
			  __I2C_ODR &= ~(SDA|SCL);	\
			  __I2C_DAT |= (SDA|SCL);	\
			  __I2C_DIR|=(SDA|SCL);	}
#define	I2C_READ	((__I2C_DAT & SDA) ? 1 : 0)
#define	I2C_SDA(x)	{ if (x) __I2C_DAT |= SDA; else __I2C_DAT &= ~SDA; }
#define	I2C_SCL(x)	{ if (x) __I2C_DAT |= SCL; else __I2C_DAT &= ~SCL; }
#define	I2C_DELAY	{ udelay(5); }
#define	I2C_ACTIVE	{ __I2C_DIR |= SDA; }
#define	I2C_TRISTATE	{ __I2C_DIR &= ~SDA; }

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/*-----------------------------------------------------------------------
 * defines we need to get FEC running
 */
#define CONFIG_FEC_ENET		1	/* Ethernet only via FEC	*/
#define	FEC_ENET		1	/* eth.c needs it that way... */
#define CONFIG_SYS_DISCOVER_PHY	1
#define CONFIG_MII		1
#define CONFIG_MII_INIT		1
#define CONFIG_PHY_ADDR		31

/*-----------------------------------------------------------------------
 * adresses
 */
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0x80000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define CONFIG_SYS_INIT_RAM_SIZE	0x2f00	/* Size of used area in DPRAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_VPD_SIZE	256 /* size in bytes reserved for vpd buffer */
#define CONFIG_SYS_INIT_VPD_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_VPD_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_INIT_VPD_OFFSET-8)

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/* Interrupt level assignments.
*/
#define FEC_INTERRUPT	SIU_LEVEL1	/* FEC interrupt */

/*-----------------------------------------------------------------------
 * Debug Enable Register
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_DER 0					/* used in start.S */

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * set up PLPRCR (PLL, Low-Power, and Reset Control Register)
 *	12	MF		calculated	Multiplication factor
 *	4	0		0000
 *	1	SPLSS	0			System PLL lock status sticky
 *	1	TEXPS	1			Timer expired status
 *	1	0		0
 *	1	TMIST	0			Timers interrupt status
 *	1	0		0
 *	1	CSRC	0			Clock source (0=DFNH, 1=DFNL)
 *	2	LPM		00			Low-power modes
 *	1	CSR		0			Checkstop reset enable
 *	1	LOLRE	0			Loss-of-lock reset enable
 *	1	FIOPD	0			Force I/O pull down
 *	5	0		00000
 */
#define CONFIG_SYS_PLPRCR	(PLPRCR_TEXPS | ((CONFIG_SYS_MF-1)<<20))

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * set up SYPCR:
 *	16	SWTC	0xffff		Software watchdog timer count
 *	8	BMT		0xff		Bus monitor timing
 *	1	BME		1			Bus monitor enable
 *	3	0		000
 *	1	SWF		1			Software watchdog freeze
 *	1	SWE		0/1			Software watchdog enable
 *	1	SWRI	0/1			Software watchdog reset/interrupt select (1=HRESET)
 *	1	SWP		0/1			Software watchdog prescale (1=/2048)
 */
#if defined (CONFIG_WATCHDOG)
 #define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
					 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
 #define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * set up SIUMCR
 *	1	EARB	0			External arbitration
 *	3	EARP	000			External arbitration request priority
 *	4	0		0000
 *	1	DSHW	0			Data show cycles
 *	2	DBGC	00			Debug pin configuration
 *	2	DBPC	00			Debug port pins configuration
 *	1	0		0
 *	1	FRC		0			FRZ pin configuration
 *	1	DLK		0			Debug register lock
 *	1	OPAR	0			Odd parity
 *	1	PNCS	0			Parity enable for non memory controller regions
 *	1	DPC		0			Data parity pins configuration
 *	1	MPRE	0			Multiprocessor reservation enable
 *	2	MLRC	11			Multi level reservation control (00=IRQ4, 01=3State, 10=KR/RETRY, 11=SPKROUT)
 *	1	AEME	0			Async external master enable
 *	1	SEME	0			Sync external master enable
 *	1	BSC		0			Byte strobe configuration
 *	1	GB5E	0			GPL_B5 enable
 *	1	B2DD	0			Bank 2 double drive
 *	1	B3DD	0			Bank 3 double drive
 *	4	0		0000
 */
#define CONFIG_SYS_SIUMCR	(SIUMCR_MLRC11)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF | PISCR_PTE)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * set up SCCR (System Clock and Reset Control Register)
 *	1	0		0
 *	2	COM		11			Clock output module (00=full, 01=half, 11=off)
 *	3	0		000
 *	1	TBS		1			Timebase source (0=OSCCLK, 1=GCLK2)
 *	1	RTDIV	0			Real-time clock divide (0=/4, 1=/512)
 *	1	RTSEL	0			Real-time clock select (0=OSCM, 1=EXTCLK)
 *	1	CRQEN	0			CPM request enable
 *	1	PRQEN	0			Power management request enable
 *	2	0		00
 *	2	EBDF	xx			External bus division factor
 *	2	0		00
 *	2	DFSYNC	00			Division factor for SYNCLK
 *	2	DFBRG	00			Division factor for BRGCLK
 *	3	DFNL	000			Division factor low frequency
 *	3	DFNH	000			Division factor high frequency
 *	5	0		00000
 */
#define SCCR_MASK	0
#ifdef CONFIG_EBDF
 #define CONFIG_SYS_SCCR	(SCCR_COM11 | SCCR_TBS | SCCR_EBDF01)
#else
 #define CONFIG_SYS_SCCR	(SCCR_COM11 | SCCR_TBS)
#endif

/*-----------------------------------------------------------------------
 * Chip Select 0 - FLASH
 *-----------------------------------------------------------------------
 * Preliminary Values
 */
/* FLASH timing: CSNT=1 ACS=10 BIH=1 SCY=4 SETA=0 TLRX=1 EHTR=1	*/
#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_4_CLK | OR_TRLX | OR_EHTR)
#define CONFIG_SYS_OR0_PRELIM	(-CONFIG_SYS_FLASH_MAX | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V )

/*-----------------------------------------------------------------------
 * misc
 *-----------------------------------------------------------------------
 *
 */
/*
 * Set the autoboot delay in seconds.  A delay of -1 disables autoboot
 */
#define CONFIG_BOOTDELAY				5

/*
 * Pass the clock frequency to the Linux kernel in units of MHz
 */
#define	CONFIG_CLOCKS_IN_MHZ

#define CONFIG_PREBOOT		\
	"echo;echo"

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND	\
	"bootp;" \
	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
	"bootm"

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE


/*
 * Set default IP stuff just to get bootstrap entries into the
 * environment so that we can source the full default environment.
 */
#define CONFIG_ETHADDR					9a:52:63:15:85:25
#define CONFIG_SERVERIP					10.0.4.200
#define CONFIG_IPADDR					10.0.4.111

#define CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

#endif	/* __CONFIG_H */
Commit	Line	Data
db2f721f WD	1	/*
	2	* (C) Copyright 2003
	3	* EMK Elektronik GmbH <www.emk-elektronik.de>
	4	* Reinhard Meyer <r.meyer@emk-elektronik.de>
	5	*
	6	* Configuation settings for the TOP860 board.
	7	*
	8	* -----------------------------------------------------------------
1a459660	9	* SPDX-License-Identifier: GPL-2.0+
db2f721f WD	10	*/
db2f721f WD	11	/*
945af8d7 WD	12	* TOP860 is a simple module:
	13	* 16-bit wide FLASH on CS0 (2MB or more)
	14	* 32-bit wide DRAM on CS2 (either 4MB or 16MB)
	15	* FEC with Am79C874 100-Base-T and Fiber Optic
	16	* Ports available, but we choose SMC1 for Console
db2f721f	17	* 8k I2C EEPROM at address 0xae, 6k user available, 2k factory set
945af8d7 WD	18	* 32768Hz crystal PLL set for 49.152MHz Core and 24.576MHz Bus Clock
	19	*
	20	* This config has been copied from MBX.h / MBX860T.h
db2f721f WD	21	*/
	22	/*
	23	* board/config.h - configuration options, board specific
	24	*/
	25
	26	#ifndef __CONFIG_H
	27	#define __CONFIG_H
	28
	29	/*
	30	* High Level Configuration Options
	31	* (easy to change)
	32	*/
	33
	34	/*-----------------------------------------------------------------------
	35	* CPU and BOARD type
	36	*/
	37	#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
	38	#define CONFIG_MPC860T 1 /* even better... an FEC! */
	39	#define CONFIG_TOP860 1 /* ...on a TOP860 module */
2ae18241 WD	40
	41	#define CONFIG_SYS_TEXT_BASE 0x80000000
	42
db2f721f	43	#undef CONFIG_WATCHDOG /* watchdog disabled */
945af8d7	44	#define CONFIG_IDENT_STRING " EMK TOP860"
db2f721f WD	45
	46	/*-----------------------------------------------------------------------
	47	* CLOCK settings
	48	*/
945af8d7	49	#define CONFIG_SYSCLK 49152000
6d0f6bcf	50	#define CONFIG_SYS_XTAL 32768
945af8d7 WD	51	#define CONFIG_EBDF 1
	52	#define CONFIG_COM 3
	53	#define CONFIG_RTC_MPC8xx
	54
db2f721f WD	55	/*-----------------------------------------------------------------------
	56	* Physical memory map as defined by EMK
	57	*/
6d0f6bcf JCPV	58	#define CONFIG_SYS_IMMR 0xFFF00000 /* Internal Memory Mapped Register */
	59	#define CONFIG_SYS_FLASH_BASE 0x80000000 /* FLASH in final mapping */
	60	#define CONFIG_SYS_DRAM_BASE 0x00000000 /* DRAM in final mapping */
	61	#define CONFIG_SYS_FLASH_MAX 0x00400000 /* max FLASH to expect */
	62	#define CONFIG_SYS_DRAM_MAX 0x01000000 /* max DRAM to expect */
945af8d7	63
db2f721f WD	64	/*-----------------------------------------------------------------------
	65	* derived values
	66	*/
6d0f6bcf JCPV	67	#define CONFIG_SYS_MF (CONFIG_SYSCLK/CONFIG_SYS_XTAL)
	68	#define CONFIG_SYS_CPUCLOCK CONFIG_SYSCLK
	69	#define CONFIG_SYS_BRGCLOCK CONFIG_SYSCLK
	70	#define CONFIG_SYS_BUSCLOCK (CONFIG_SYSCLK >> CONFIG_EBDF)
	71	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
945af8d7 WD	72	#define CONFIG_8xx_GCLK_FREQ CONFIG_SYSCLK
945af8d7 WD	73
db2f721f WD	74	/*-----------------------------------------------------------------------
	75	* FLASH organization
	76	*/
6d0f6bcf JCPV	77	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	78	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
db2f721f	79
6d0f6bcf JCPV	80	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	81	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
945af8d7	82
6d0f6bcf	83	#define CONFIG_SYS_FLASH_CFI
db2f721f WD	84
	85	/*-----------------------------------------------------------------------
	86	* Command interpreter
	87	*/
	88	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	89	#undef CONFIG_8xx_CONS_SMC2
	90	#define CONFIG_BAUDRATE 9600
945af8d7	91
db2f721f WD	92	/*
	93	* Allow partial commands to be matched to uniqueness.
	94	*/
6d0f6bcf	95	#define CONFIG_SYS_MATCH_PARTIAL_CMD
db2f721f	96
a5562901	97
db2f721f	98	/*
a5562901	99	* Command line configuration.
db2f721f	100	*/
a5562901 JL	101	#include <config_cmd_default.h>
	102
	103	#define CONFIG_CMD_ASKENV
	104	#define CONFIG_CMD_DHCP
	105	#define CONFIG_CMD_I2C
	106	#define CONFIG_CMD_EEPROM
	107	#define CONFIG_CMD_REGINFO
	108	#define CONFIG_CMD_IMMAP
	109	#define CONFIG_CMD_ELF
	110	#define CONFIG_CMD_DATE
	111	#define CONFIG_CMD_MII
	112	#define CONFIG_CMD_BEDBUG
	113
db2f721f	114
74de7aef	115	#define CONFIG_SOURCE 1
6d0f6bcf	116	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
db2f721f WD	117	#undef CONFIG_LOADS_ECHO /* NO echo on for serial download */
db2f721f WD	118
db2f721f	119
6d0f6bcf JCPV	120	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	121	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
945af8d7	122
6d0f6bcf	123	#undef CONFIG_SYS_HUSH_PARSER /* Hush parse for U-Boot */
945af8d7	124
945af8d7	125
a5562901	126	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	127	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
db2f721f	128	#else
6d0f6bcf	129	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
db2f721f	130	#endif
945af8d7	131
6d0f6bcf JCPV	132	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	133	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	134	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
db2f721f WD	135
	136	/*-----------------------------------------------------------------------
	137	* Memory Test Command
	138	*/
6d0f6bcf JCPV	139	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	140	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
945af8d7	141
db2f721f WD	142	/*-----------------------------------------------------------------------
	143	* Environment handler
	144	* only the first 6k in EEPROM are available for user. Of that we use 256b
	145	*/
bb1f8b4f	146	#define CONFIG_ENV_IS_IN_EEPROM 1 /* turn on EEPROM env feature */
0e8d1586 JCPV	147	#define CONFIG_ENV_OFFSET 0x1000
0e8d1586 JCPV	148	#define CONFIG_ENV_SIZE 0x0700
6d0f6bcf JCPV	149	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
	150	#define CONFIG_SYS_FACT_OFFSET 0x1800
	151	#define CONFIG_SYS_FACT_SIZE 0x0800
	152	#define CONFIG_SYS_I2C_FACT_ADDR 0x57
	153	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	154	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	155	#define CONFIG_SYS_EEPROM_SIZE 0x2000
6d0f6bcf	156	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12
945af8d7 WD	157	#define CONFIG_ENV_OVERWRITE
	158	#define CONFIG_MISC_INIT_R
	159
ea818dbb HS	160	#define CONFIG_SYS_I2C
	161	#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
	162	#define CONFIG_SYS_I2C_SOFT_SPEED 100000
	163	#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
	164	/**/
945af8d7 WD	165	#define SDA 0x00010
945af8d7 WD	166	#define SCL 0x00020
f57f70aa WD	167	#define __I2C_DIR immr->im_cpm.cp_pbdir
	168	#define __I2C_DAT immr->im_cpm.cp_pbdat
	169	#define __I2C_PAR immr->im_cpm.cp_pbpar
	170	#define __I2C_ODR immr->im_cpm.cp_pbodr
	171	#define I2C_INIT { __I2C_PAR &= ~(SDA\|SCL); \
	172	__I2C_ODR &= ~(SDA\|SCL); \
	173	__I2C_DAT \|= (SDA\|SCL); \
	174	__I2C_DIR\|=(SDA\|SCL); }
	175	#define I2C_READ ((__I2C_DAT & SDA) ? 1 : 0)
	176	#define I2C_SDA(x) { if (x) __I2C_DAT \|= SDA; else __I2C_DAT &= ~SDA; }
	177	#define I2C_SCL(x) { if (x) __I2C_DAT \|= SCL; else __I2C_DAT &= ~SCL; }
	178	#define I2C_DELAY { udelay(5); }
	179	#define I2C_ACTIVE { __I2C_DIR \|= SDA; }
	180	#define I2C_TRISTATE { __I2C_DIR &= ~SDA; }
db2f721f	181
6d0f6bcf	182	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
db2f721f WD	183
	184	/*-----------------------------------------------------------------------
	185	* defines we need to get FEC running
945af8d7	186	*/
53677ef1 WD	187	#define CONFIG_FEC_ENET 1 /* Ethernet only via FEC */
53677ef1 WD	188	#define FEC_ENET 1 /* eth.c needs it that way... */
6d0f6bcf	189	#define CONFIG_SYS_DISCOVER_PHY 1
53677ef1	190	#define CONFIG_MII 1
0f3ba7e9	191	#define CONFIG_MII_INIT 1
db2f721f	192	#define CONFIG_PHY_ADDR 31
945af8d7	193
db2f721f WD	194	/*-----------------------------------------------------------------------
db2f721f WD	195	* adresses
945af8d7	196	*/
6d0f6bcf	197	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
14d0a02a	198	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf	199	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
945af8d7	200
db2f721f WD	201	/*-----------------------------------------------------------------------
	202	* Start addresses for the final memory configuration
	203	* (Set up by the startup code)
6d0f6bcf	204	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
db2f721f	205	*/
6d0f6bcf JCPV	206	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	207	#define CONFIG_SYS_FLASH_BASE 0x80000000
945af8d7	208
db2f721f WD	209	/*-----------------------------------------------------------------------
	210	* Definitions for initial stack pointer and data area (in DPRAM)
	211	*/
6d0f6bcf	212	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	213	#define CONFIG_SYS_INIT_RAM_SIZE 0x2f00 /* Size of used area in DPRAM */
25ddd1fb	214	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf JCPV	215	#define CONFIG_SYS_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */
	216	#define CONFIG_SYS_INIT_VPD_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_VPD_SIZE)
	217	#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_VPD_OFFSET-8)
db2f721f WD	218
	219	/*-----------------------------------------------------------------------
	220	* Cache Configuration
	221	*/
6d0f6bcf	222	#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
a5562901	223	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	224	#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
db2f721f WD	225	#endif
	226
	227	/* Interrupt level assignments.
	228	*/
	229	#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
	230
db2f721f WD	231	/*-----------------------------------------------------------------------
	232	* Debug Enable Register
	233	*-----------------------------------------------------------------------
	234	*
	235	*/
6d0f6bcf	236	#define CONFIG_SYS_DER 0 /* used in start.S */
db2f721f WD	237
	238	/*-----------------------------------------------------------------------
	239	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	240	*-----------------------------------------------------------------------
945af8d7 WD	241	* set up PLPRCR (PLL, Low-Power, and Reset Control Register)
	242	* 12 MF calculated Multiplication factor
	243	* 4 0 0000
	244	* 1 SPLSS 0 System PLL lock status sticky
	245	* 1 TEXPS 1 Timer expired status
	246	* 1 0 0
	247	* 1 TMIST 0 Timers interrupt status
	248	* 1 0 0
	249	* 1 CSRC 0 Clock source (0=DFNH, 1=DFNL)
	250	* 2 LPM 00 Low-power modes
	251	* 1 CSR 0 Checkstop reset enable
	252	* 1 LOLRE 0 Loss-of-lock reset enable
	253	* 1 FIOPD 0 Force I/O pull down
42d1f039	254	* 5 0 00000
db2f721f	255	*/
6d0f6bcf	256	#define CONFIG_SYS_PLPRCR (PLPRCR_TEXPS \| ((CONFIG_SYS_MF-1)<<20))
945af8d7	257
db2f721f WD	258	/*-----------------------------------------------------------------------
	259	* SYPCR - System Protection Control 11-9
	260	* SYPCR can only be written once after reset!
	261	*-----------------------------------------------------------------------
945af8d7 WD	262	* set up SYPCR:
945af8d7 WD	263	* 16 SWTC 0xffff Software watchdog timer count
53677ef1	264	* 8 BMT 0xff Bus monitor timing
945af8d7 WD	265	* 1 BME 1 Bus monitor enable
	266	* 3 0 000
	267	* 1 SWF 1 Software watchdog freeze
	268	* 1 SWE 0/1 Software watchdog enable
	269	* 1 SWRI 0/1 Software watchdog reset/interrupt select (1=HRESET)
	270	* 1 SWP 0/1 Software watchdog prescale (1=/2048)
db2f721f WD	271	*/
db2f721f WD	272	#if defined (CONFIG_WATCHDOG)
6d0f6bcf	273	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
53677ef1	274	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
db2f721f	275	#else
6d0f6bcf	276	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF)
db2f721f WD	277	#endif
	278
	279	/*-----------------------------------------------------------------------
	280	* SIUMCR - SIU Module Configuration 11-6
	281	*-----------------------------------------------------------------------
945af8d7 WD	282	* set up SIUMCR
	283	* 1 EARB 0 External arbitration
	284	* 3 EARP 000 External arbitration request priority
	285	* 4 0 0000
	286	* 1 DSHW 0 Data show cycles
	287	* 2 DBGC 00 Debug pin configuration
	288	* 2 DBPC 00 Debug port pins configuration
	289	* 1 0 0
	290	* 1 FRC 0 FRZ pin configuration
	291	* 1 DLK 0 Debug register lock
	292	* 1 OPAR 0 Odd parity
	293	* 1 PNCS 0 Parity enable for non memory controller regions
	294	* 1 DPC 0 Data parity pins configuration
	295	* 1 MPRE 0 Multiprocessor reservation enable
	296	* 2 MLRC 11 Multi level reservation control (00=IRQ4, 01=3State, 10=KR/RETRY, 11=SPKROUT)
	297	* 1 AEME 0 Async external master enable
	298	* 1 SEME 0 Sync external master enable
	299	* 1 BSC 0 Byte strobe configuration
	300	* 1 GB5E 0 GPL_B5 enable
42d1f039 WD	301	* 1 B2DD 0 Bank 2 double drive
42d1f039 WD	302	* 1 B3DD 0 Bank 3 double drive
945af8d7	303	* 4 0 0000
db2f721f	304	*/
6d0f6bcf	305	#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC11)
945af8d7	306
db2f721f WD	307	/*-----------------------------------------------------------------------
	308	* TBSCR - Time Base Status and Control 11-26
	309	*-----------------------------------------------------------------------
	310	* Clear Reference Interrupt Status, Timebase freezing enabled
	311	*/
6d0f6bcf	312	#define CONFIG_SYS_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
db2f721f WD	313
	314	/*-----------------------------------------------------------------------
	315	* PISCR - Periodic Interrupt Status and Control 11-31
	316	*-----------------------------------------------------------------------
	317	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	318	*/
6d0f6bcf	319	#define CONFIG_SYS_PISCR (PISCR_PS \| PISCR_PITF \| PISCR_PTE)
db2f721f WD	320
	321	/*-----------------------------------------------------------------------
	322	* SCCR - System Clock and reset Control Register 15-27
	323	*-----------------------------------------------------------------------
945af8d7 WD	324	* set up SCCR (System Clock and Reset Control Register)
	325	* 1 0 0
	326	* 2 COM 11 Clock output module (00=full, 01=half, 11=off)
	327	* 3 0 000
	328	* 1 TBS 1 Timebase source (0=OSCCLK, 1=GCLK2)
	329	* 1 RTDIV 0 Real-time clock divide (0=/4, 1=/512)
	330	* 1 RTSEL 0 Real-time clock select (0=OSCM, 1=EXTCLK)
	331	* 1 CRQEN 0 CPM request enable
	332	* 1 PRQEN 0 Power management request enable
	333	* 2 0 00
	334	* 2 EBDF xx External bus division factor
	335	* 2 0 00
	336	* 2 DFSYNC 00 Division factor for SYNCLK
	337	* 2 DFBRG 00 Division factor for BRGCLK
	338	* 3 DFNL 000 Division factor low frequency
	339	* 3 DFNH 000 Division factor high frequency
	340	* 5 0 00000
db2f721f WD	341	*/
db2f721f WD	342	#define SCCR_MASK 0
42dfe7a1	343	#ifdef CONFIG_EBDF
6d0f6bcf	344	#define CONFIG_SYS_SCCR (SCCR_COM11 \| SCCR_TBS \| SCCR_EBDF01)
945af8d7	345	#else
6d0f6bcf	346	#define CONFIG_SYS_SCCR (SCCR_COM11 \| SCCR_TBS)
945af8d7	347	#endif
db2f721f WD	348
	349	/*-----------------------------------------------------------------------
	350	* Chip Select 0 - FLASH
	351	*-----------------------------------------------------------------------
	352	* Preliminary Values
	353	*/
	354	/* FLASH timing: CSNT=1 ACS=10 BIH=1 SCY=4 SETA=0 TLRX=1 EHTR=1 */
6d0f6bcf JCPV	355	#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM \| OR_ACS_DIV4 \| OR_BI \| OR_SCY_4_CLK \| OR_TRLX \| OR_EHTR)
	356	#define CONFIG_SYS_OR0_PRELIM (-CONFIG_SYS_FLASH_MAX \| CONFIG_SYS_OR_TIMING_FLASH)
	357	#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \| BR_PS_16 \| BR_V )
945af8d7	358
db2f721f WD	359	/*-----------------------------------------------------------------------
	360	* misc
	361	*-----------------------------------------------------------------------
	362	*
	363	*/
	364	/*
	365	* Set the autoboot delay in seconds. A delay of -1 disables autoboot
	366	*/
	367	#define CONFIG_BOOTDELAY 5
	368
	369	/*
	370	* Pass the clock frequency to the Linux kernel in units of MHz
	371	*/
	372	#define CONFIG_CLOCKS_IN_MHZ
	373
	374	#define CONFIG_PREBOOT \
	375	"echo;echo"
	376
	377	#undef CONFIG_BOOTARGS
	378	#define CONFIG_BOOTCOMMAND \
	379	"bootp;" \
fe126d8b WD	380	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
fe126d8b WD	381	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
db2f721f WD	382	"bootm"
	383
	384	/*
	385	* BOOTP options
	386	*/
37d4bb70 JL	387	#define CONFIG_BOOTP_SUBNETMASK
	388	#define CONFIG_BOOTP_GATEWAY
	389	#define CONFIG_BOOTP_HOSTNAME
	390	#define CONFIG_BOOTP_BOOTPATH
	391	#define CONFIG_BOOTP_BOOTFILESIZE
42d1f039	392
db2f721f WD	393
	394	/*
	395	* Set default IP stuff just to get bootstrap entries into the
74de7aef	396	* environment so that we can source the full default environment.
db2f721f WD	397	*/
	398	#define CONFIG_ETHADDR 9a:52:63:15:85:25
	399	#define CONFIG_SERVERIP 10.0.4.200
	400	#define CONFIG_IPADDR 10.0.4.111
945af8d7	401
6d0f6bcf	402	#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
945af8d7	403
db2f721f WD	404	/*
	405	* For booting Linux, the board info and command line data
	406	* have to be in the first 8 MB of memory, since this is
	407	* the maximum mapped by the Linux kernel during initialization.
	408	*/
6d0f6bcf	409	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
db2f721f	410
db2f721f	411	#endif /* __CONFIG_H */