[J-u-boot.git] / include / configs / PCI5441.h

/*
 * (C) Copyright 2004, Psyent Corporation <www.psyent.com>
 * Scott McNutt <smcnutt@psyent.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*------------------------------------------------------------------------
 * BOARD/CPU
 *----------------------------------------------------------------------*/
#define	CONFIG_PCI5441		1		/* PCI-5441 board	*/
#define CONFIG_SYS_CLK_FREQ	50000000	/* 50 MHz core clk	*/

#define CONFIG_SYS_RESET_ADDR		0x00000000	/* Hard-reset address	*/
#define CONFIG_SYS_EXCEPTION_ADDR	0x01000020	/* Exception entry point*/
#define CONFIG_SYS_NIOS_SYSID_BASE	0x00920828	/* System id address	*/
#define	CONFIG_BOARD_EARLY_INIT_F 1	/* enable early board-spec. init*/

/*------------------------------------------------------------------------
 * CACHE -- the following will support II/s and II/f. The II/s does not
 * have dcache, so the cache instructions will behave as NOPs.
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_ICACHE_SIZE		4096		/* 4 KByte total	*/
#define CONFIG_SYS_ICACHELINE_SIZE	32		/* 32 bytes/line	*/
#define CONFIG_SYS_DCACHE_SIZE		2048		/* 2 KByte (II/f)	*/
#define CONFIG_SYS_DCACHELINE_SIZE	4		/* 4 bytes/line (II/f)	*/

/*------------------------------------------------------------------------
 * MEMORY BASE ADDRESSES
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_FLASH_BASE		0x00000000	/* FLASH base addr	*/
#define CONFIG_SYS_FLASH_SIZE		0x00800000	/* 8 MByte		*/
#define CONFIG_SYS_SDRAM_BASE		0x01000000	/* SDRAM base addr	*/
#define CONFIG_SYS_SDRAM_SIZE		0x01000000	/* 16 MByte		*/

/*------------------------------------------------------------------------
 * MEMORY ORGANIZATION
 *	-Monitor at top.
 *	-The heap is placed below the monitor.
 *	-Global data is placed below the heap.
 *	-The stack is placed below global data (&grows down).
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_MONITOR_LEN		(128 * 1024)	/* Reserve 128k		*/
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_MALLOC_BASE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP		CONFIG_SYS_GBL_DATA_OFFSET

/*------------------------------------------------------------------------
 * FLASH (AM29LV065D)
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_MAX_FLASH_SECT	128		/* Max # sects per bank */
#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* Max # of flash banks */
#define CONFIG_SYS_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned char	/* flash word size	*/

/*------------------------------------------------------------------------
 * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
 * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
 * reset address, no? This will keep the environment in user region
 * of flash. NOTE: the monitor length must be multiple of sector size
 * (which is common practice).
 *----------------------------------------------------------------------*/
#define	CONFIG_ENV_IS_IN_FLASH	1		/* Environment in flash */
#define CONFIG_ENV_SIZE		(64 * 1024)	/* 64 KByte (1 sector)	*/
#define CONFIG_ENV_OVERWRITE			/* Serial change Ok	*/
#define CONFIG_ENV_ADDR	(CONFIG_SYS_RESET_ADDR + CONFIG_SYS_MONITOR_LEN)

/*------------------------------------------------------------------------
 * CONSOLE
 *----------------------------------------------------------------------*/
#define CONFIG_ALTERA_UART		1	/* Use altera uart */
#if defined(CONFIG_ALTERA_JTAG_UART)
#define CONFIG_SYS_NIOS_CONSOLE	0x00920820	/* JTAG UART base addr	*/
#else
#define CONFIG_SYS_NIOS_CONSOLE	0x009208a0	/* UART base addr	*/
#endif

#define CONFIG_SYS_NIOS_FIXEDBAUD	1		/* Baudrate is fixed	*/
#define CONFIG_BAUDRATE		115200		/* Initial baudrate	*/
#define CONFIG_SYS_BAUDRATE_TABLE	{115200}	/* It's fixed ;-)	*/

#define CONFIG_SYS_CONSOLE_INFO_QUIET	1		/* Suppress console info*/

/*------------------------------------------------------------------------
 * DEBUG
 *----------------------------------------------------------------------*/
#undef CONFIG_ROM_STUBS				/* Stubs not in ROM	*/

/*------------------------------------------------------------------------
 * TIMEBASE --
 *
 * The high res timer defaults to 1 msec. Since it includes the period
 * registers, the interrupt frequency can be reduced using TMRCNT.
 * If the default period is acceptable, TMRCNT can be left undefined.
 * TMRMS represents the desired mecs per tick (msecs per interrupt).
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_HZ			1000	/* Always 1000 */
#define CONFIG_SYS_LOW_RES_TIMER
#define CONFIG_SYS_NIOS_TMRBASE	0x00920860	/* Tick timer base addr	*/
#define CONFIG_SYS_NIOS_TMRIRQ		3	/* Timer IRQ num */
#define CONFIG_SYS_NIOS_TMRMS		10	/* Desired period (msec)*/
#define CONFIG_SYS_NIOS_TMRCNT \
		(CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#define CONFIG_CMD_BDI
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
#define CONFIG_CMD_RUN
#define CONFIG_CMD_SAVES


/*------------------------------------------------------------------------
 * MISC
 *----------------------------------------------------------------------*/
#define	CONFIG_SYS_LONGHELP				/* Provide extended help*/
#define	CONFIG_SYS_PROMPT		"==> "		/* Command prompt	*/
#define	CONFIG_SYS_CBSIZE		256		/* Console I/O buf size	*/
#define	CONFIG_SYS_MAXARGS		16		/* Max command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot arg buf size	*/
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buf size	*/
#define	CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE	/* Default load address	*/
#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE	/* Start addr for test	*/
#define CONFIG_SYS_MEMTEST_END		CONFIG_SYS_INIT_SP - 0x00020000

#endif	/* __CONFIG_H */
Commit	Line	Data
5c952cf0 WD	1	/*
	2	* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
	3	* Scott McNutt <smcnutt@psyent.com>
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
5c952cf0 WD	6	*/
	7
	8	#ifndef __CONFIG_H
	9	#define __CONFIG_H
	10
	11	/*------------------------------------------------------------------------
	12	* BOARD/CPU
	13	----------------------------------------------------------------------/
	14	#define CONFIG_PCI5441 1 /* PCI-5441 board */
	15	#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */
	16
6d0f6bcf JCPV	17	#define CONFIG_SYS_RESET_ADDR 0x00000000 /* Hard-reset address */
	18	#define CONFIG_SYS_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/
	19	#define CONFIG_SYS_NIOS_SYSID_BASE 0x00920828 /* System id address */
5c952cf0 WD	20	#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/
	21
	22	/*------------------------------------------------------------------------
	23	* CACHE -- the following will support II/s and II/f. The II/s does not
	24	* have dcache, so the cache instructions will behave as NOPs.
	25	----------------------------------------------------------------------/
6d0f6bcf JCPV	26	#define CONFIG_SYS_ICACHE_SIZE 4096 /* 4 KByte total */
	27	#define CONFIG_SYS_ICACHELINE_SIZE 32 /* 32 bytes/line */
	28	#define CONFIG_SYS_DCACHE_SIZE 2048 /* 2 KByte (II/f) */
	29	#define CONFIG_SYS_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */
5c952cf0 WD	30
	31	/*------------------------------------------------------------------------
	32	* MEMORY BASE ADDRESSES
	33	----------------------------------------------------------------------/
6d0f6bcf JCPV	34	#define CONFIG_SYS_FLASH_BASE 0x00000000 /* FLASH base addr */
	35	#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */
	36	#define CONFIG_SYS_SDRAM_BASE 0x01000000 /* SDRAM base addr */
	37	#define CONFIG_SYS_SDRAM_SIZE 0x01000000 /* 16 MByte */
5c952cf0 WD	38
	39	/*------------------------------------------------------------------------
	40	* MEMORY ORGANIZATION
53677ef1 WD	41	* -Monitor at top.
	42	* -The heap is placed below the monitor.
	43	* -Global data is placed below the heap.
	44	* -The stack is placed below global data (&grows down).
5c952cf0	45	----------------------------------------------------------------------/
6d0f6bcf	46	#define CONFIG_SYS_MONITOR_LEN (128 * 1024) /* Reserve 128k */
6d0f6bcf	47	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
5c952cf0	48
14d0a02a	49	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf	50	#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
25ddd1fb	51	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	52	#define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET
5c952cf0 WD	53
	54	/*------------------------------------------------------------------------
	55	* FLASH (AM29LV065D)
	56	----------------------------------------------------------------------/
6d0f6bcf JCPV	57	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max # sects per bank */
	58	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max # of flash banks */
	59	#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */
	60	#define CONFIG_SYS_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */
	61	#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size */
5c952cf0 WD	62
5c952cf0 WD	63	/*------------------------------------------------------------------------
6d0f6bcf JCPV	64	* ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
6d0f6bcf JCPV	65	* CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
5c952cf0 WD	66	* reset address, no? This will keep the environment in user region
	67	* of flash. NOTE: the monitor length must be multiple of sector size
	68	* (which is common practice).
	69	----------------------------------------------------------------------/
5a1aceb0	70	#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment in flash */
0e8d1586	71	#define CONFIG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */
5c952cf0	72	#define CONFIG_ENV_OVERWRITE /* Serial change Ok */
6d0f6bcf	73	#define CONFIG_ENV_ADDR (CONFIG_SYS_RESET_ADDR + CONFIG_SYS_MONITOR_LEN)
5c952cf0 WD	74
	75	/*------------------------------------------------------------------------
	76	* CONSOLE
	77	----------------------------------------------------------------------/
c9d4f46b SM	78	#define CONFIG_ALTERA_UART 1 /* Use altera uart */
c9d4f46b SM	79	#if defined(CONFIG_ALTERA_JTAG_UART)
6d0f6bcf	80	#define CONFIG_SYS_NIOS_CONSOLE 0x00920820 /* JTAG UART base addr */
5c952cf0	81	#else
6d0f6bcf	82	#define CONFIG_SYS_NIOS_CONSOLE 0x009208a0 /* UART base addr */
5c952cf0 WD	83	#endif
5c952cf0 WD	84
6d0f6bcf	85	#define CONFIG_SYS_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */
5c952cf0	86	#define CONFIG_BAUDRATE 115200 /* Initial baudrate */
6d0f6bcf	87	#define CONFIG_SYS_BAUDRATE_TABLE {115200} /* It's fixed ;-) */
5c952cf0	88
6d0f6bcf	89	#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Suppress console info*/
5c952cf0 WD	90
	91	/*------------------------------------------------------------------------
	92	* DEBUG
	93	----------------------------------------------------------------------/
	94	#undef CONFIG_ROM_STUBS /* Stubs not in ROM */
	95
	96	/*------------------------------------------------------------------------
	97	* TIMEBASE --
	98	*
	99	* The high res timer defaults to 1 msec. Since it includes the period
3a89a91a SM	100	* registers, the interrupt frequency can be reduced using TMRCNT.
	101	* If the default period is acceptable, TMRCNT can be left undefined.
	102	* TMRMS represents the desired mecs per tick (msecs per interrupt).
5c952cf0	103	----------------------------------------------------------------------/
3a89a91a	104	#define CONFIG_SYS_HZ 1000 /* Always 1000 */
e110c4fe	105	#define CONFIG_SYS_LOW_RES_TIMER
6d0f6bcf	106	#define CONFIG_SYS_NIOS_TMRBASE 0x00920860 /* Tick timer base addr */
3a89a91a SM	107	#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */
	108	#define CONFIG_SYS_NIOS_TMRMS 10 /* Desired period (msec)*/
	109	#define CONFIG_SYS_NIOS_TMRCNT \
	110	(CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
5c952cf0	111
acf02697	112
a1aa0bb5 JL	113	/*
	114	* BOOTP options
	115	*/
	116	#define CONFIG_BOOTP_BOOTFILESIZE
	117	#define CONFIG_BOOTP_BOOTPATH
	118	#define CONFIG_BOOTP_GATEWAY
	119	#define CONFIG_BOOTP_HOSTNAME
	120
	121
acf02697 JL	122	/*
	123	* Command line configuration.
	124	*/
	125	#define CONFIG_CMD_BDI
	126	#define CONFIG_CMD_ECHO
bdab39d3	127	#define CONFIG_CMD_SAVEENV
acf02697 JL	128	#define CONFIG_CMD_FLASH
	129	#define CONFIG_CMD_IMI
	130	#define CONFIG_CMD_IRQ
	131	#define CONFIG_CMD_LOADS
	132	#define CONFIG_CMD_LOADB
	133	#define CONFIG_CMD_MEMORY
	134	#define CONFIG_CMD_MISC
	135	#define CONFIG_CMD_RUN
	136	#define CONFIG_CMD_SAVES
	137
5c952cf0 WD	138
	139	/*------------------------------------------------------------------------
	140	* MISC
	141	----------------------------------------------------------------------/
6d0f6bcf JCPV	142	#define CONFIG_SYS_LONGHELP /* Provide extended help*/
	143	#define CONFIG_SYS_PROMPT "==> " /* Command prompt */
	144	#define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */
	145	#define CONFIG_SYS_MAXARGS 16 /* Max command args */
	146	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg buf size */
	147	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buf size */
	148	#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* Default load address */
	149	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* Start addr for test */
	150	#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_INIT_SP - 0x00020000
5c952cf0 WD	151
5c952cf0 WD	152	#endif /* __CONFIG_H */