[J-u-boot.git] / include / configs / MHPC.h

/*
 * (C) Copyright 2001
 * Frank Gottschling, ELTEC Elektronik AG, fgottschling@eltec.de
 *
 * (C) Copyright 2001
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * Configuation settings for the miniHiPerCam.
 *
 * -----------------------------------------------------------------
 * SPDX-License-Identifier:	GPL-2.0+ 
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
#define CONFIG_MHPC		1	/* on a miniHiPerCam		*/
#define CONFIG_BOARD_EARLY_INIT_F 1	/* do special hardware init.	*/
#define CONFIG_MISC_INIT_R	1

#define	CONFIG_SYS_TEXT_BASE	0xfe000000

#define CONFIG_8xx_GCLK_FREQ	MPC8XX_SPEED
#undef	CONFIG_8xx_CONS_SMC1
#define CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC2		*/
#undef	CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE		9600
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/

#define CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */

#define CONFIG_ENV_OVERWRITE	1
#define CONFIG_ETHADDR		00:00:5b:ee:de:ad

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND	\
	"bootp;"								\
	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
	"bootm"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
#define CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/

#undef	CONFIG_UCODE_PATCH

/* enable I2C and select the hardware/software driver */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
#define CONFIG_SYS_I2C_SOFT_SPEED	50000
#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
/*
 * Software (bit-bang) I2C driver configuration
 */
#define PB_SCL		0x00000020	/* PB 26 */
#define PB_SDA		0x00000010	/* PB 27 */

#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
			else	immr->im_cpm.cp_pbdat &= ~PB_SDA
#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
			else	immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */

#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* EEPROM X24C04		*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1	/* bytes of address		*/
/* mask of address bits that overflow into the "EEPROM chip address"	*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10

#define LCD_VIDEO_ADDR		(SDRAM_MAX_SIZE-SDRAM_RES_SIZE)
#define LCD_VIDEO_SIZE		SDRAM_RES_SIZE	/* 2MB */
#define LCD_VIDEO_COLS		640
#define LCD_VIDEO_ROWS		480
#define LCD_VIDEO_FG		255
#define LCD_VIDEO_BG		0

#undef	CONFIG_VIDEO				/* test only ! s.a devices.c and 8xx */
#define CONFIG_CFB_CONSOLE			/* framebuffer console with std input */
#define CONFIG_VIDEO_LOGO

#define VIDEO_KBD_INIT_FCT	0		/* no KBD dev on MHPC - use serial */
#define VIDEO_TSTC_FCT		serial_tstc
#define VIDEO_GETC_FCT		serial_getc

#define CONFIG_BR0_WORKAROUND	1


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DATE
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_REGINFO


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE


/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define CONFIG_SYS_LOAD_ADDR		0x300000	/* default load address */

#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

/*-----------------------------------------------------------------------
 * Physical memory map
 */
#define CONFIG_SYS_IMMR		0xFFF00000 /* Internal Memory Mapped Register*/

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0xfe000000

#define CONFIG_SYS_MONITOR_LEN		0x40000		/* Reserve 256 kB for Monitor	*/
#undef	CONFIG_SYS_MONITOR_BASE		    /* to run U-Boot from RAM */
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * JFFS2 partitions
 *
 */
/* No command line, one static partition, whole device */
#undef CONFIG_CMD_MTDPARTS
#define CONFIG_JFFS2_DEV		"nor0"
#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
#define CONFIG_JFFS2_PART_OFFSET	0x00000000

/* mtdparts command line support */
/* Note: fake mtd_id used, no linux mtd map file */
/*
#define CONFIG_CMD_MTDPARTS
#define MTDIDS_DEFAULT		"nor0=mhpc-0"
#define MTDPARTS_DEFAULT	"mtdparts=mhpc-0:-(jffs2)"
*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map- for Linux	*/

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_OFFSET		CONFIG_SYS_MONITOR_LEN /* Offset of Environment */
#define CONFIG_ENV_SIZE		0x20000 /* Total Size of Environment	*/

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#define CONFIG_SYS_SIUMCR	(SIUMCR_SEME)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF | PISCR_PTE)

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register		12-18
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit - leave PLL multiplication factor unchanged !
 */
#define MPC8XX_SPEED	50000000L
#define MPC8XX_XIN	5000000L      /* ref clk */
#define MPC8XX_FACT	(MPC8XX_SPEED/MPC8XX_XIN)
#define CONFIG_SYS_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
			PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */

#define SCCR_MASK	(SCCR_RTDIV | SCCR_RTSEL)     /* SCCR_EBDF11 */
#define CONFIG_SYS_SCCR	(SCCR_TBS | SCCR_DFLCD001)


/*-----------------------------------------------------------------------
 * MAMR settings for SDRAM	- 16-14
 * => 0xC080200F
 *-----------------------------------------------------------------------
 * periodic timer for refresh
 */
#define CONFIG_SYS_MAMR_PTA	0xC0
#define CONFIG_SYS_MAMR	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | MAMR_G0CLA_A11 | MAMR_TLFA_MSK)

/*
 * BR0 and OR0 (FLASH) used to re-map FLASH
 */

/* allow for max 8 MB of Flash */
#define FLASH_BASE		0xFE000000	/* FLASH bank #0*/
#define FLASH_BASE0_PRELIM	0xFE000000	/* FLASH bank #0*/
#define CONFIG_SYS_REMAP_OR_AM		0xFF800000	/* OR addr mask */
#define CONFIG_SYS_PRELIM_OR_AM	0xFF800000	/* OR addr mask */

#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK) /* (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)*/

#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V )

/*
 * BR1 and OR1 (SDRAM)
 */
#define SDRAM_BASE1_PRELIM	0x00000000	/* SDRAM bank #0	*/
#define SDRAM_MAX_SIZE		0x01000000	/* max 16 MB		*/
#define SDRAM_RES_SIZE		0x00200000	/* 2 MB for framebuffer */

/* SDRAM timing: drive GPL5 high on first cycle */
#define CONFIG_SYS_OR_TIMING_SDRAM	(OR_G5LS)

#define CONFIG_SYS_OR1_PRELIM	((~(SDRAM_MAX_SIZE)+1)| CONFIG_SYS_OR_TIMING_SDRAM )
#define CONFIG_SYS_BR1_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )

/*
 * BR2/OR2 - DIMM
 */
#define CONFIG_SYS_OR2		(OR_ACS_DIV4)
#define CONFIG_SYS_BR2		(BR_MS_UPMA)

/*
 * BR3/OR3 - DIMM
 */
#define CONFIG_SYS_OR3		(OR_ACS_DIV4)
#define CONFIG_SYS_BR3		(BR_MS_UPMA)

/*
 * BR4/OR4
 */
#define CONFIG_SYS_OR4		0
#define CONFIG_SYS_BR4		0

/*
 * BR5/OR5
 */
#define CONFIG_SYS_OR5		0
#define CONFIG_SYS_BR5		0

/*
 * BR6/OR6
 */
#define CONFIG_SYS_OR6		0
#define CONFIG_SYS_BR6		0

/*
 * BR7/OR7
 */
#define CONFIG_SYS_OR7		0
#define CONFIG_SYS_BR7		0


/*-----------------------------------------------------------------------
 * Debug Entry Mode
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_DER 0

#endif	/* __CONFIG_H */
Commit	Line	Data
e2211743 WD	1	/*
	2	* (C) Copyright 2001
	3	* Frank Gottschling, ELTEC Elektronik AG, fgottschling@eltec.de
	4	*
	5	* (C) Copyright 2001
	6	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	7	*
	8	* Configuation settings for the miniHiPerCam.
	9	*
	10	* -----------------------------------------------------------------
1a459660	11	* SPDX-License-Identifier: GPL-2.0+
e2211743 WD	12	*/
	13
	14	/*
	15	* board/config.h - configuration options, board specific
	16	*/
	17
	18	#ifndef __CONFIG_H
	19	#define __CONFIG_H
	20
	21	/*
	22	* High Level Configuration Options
	23	* (easy to change)
	24	*/
	25	#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
c837dcb1 WD	26	#define CONFIG_MHPC 1 /* on a miniHiPerCam */
	27	#define CONFIG_BOARD_EARLY_INIT_F 1 /* do special hardware init. */
	28	#define CONFIG_MISC_INIT_R 1
e2211743	29
2ae18241 WD	30	#define CONFIG_SYS_TEXT_BASE 0xfe000000
2ae18241 WD	31
e2211743 WD	32	#define CONFIG_8xx_GCLK_FREQ MPC8XX_SPEED
e2211743 WD	33	#undef CONFIG_8xx_CONS_SMC1
c837dcb1	34	#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
e2211743 WD	35	#undef CONFIG_8xx_CONS_NONE
	36	#define CONFIG_BAUDRATE 9600
	37	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	38
c837dcb1	39	#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
e2211743	40
c837dcb1 WD	41	#define CONFIG_ENV_OVERWRITE 1
c837dcb1 WD	42	#define CONFIG_ETHADDR 00:00:5b:ee:de:ad
e2211743	43
c837dcb1	44	#undef CONFIG_BOOTARGS
e2211743 WD	45	#define CONFIG_BOOTCOMMAND \
e2211743 WD	46	"bootp;" \
fe126d8b WD	47	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
fe126d8b WD	48	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
e2211743 WD	49	"bootm"
	50
	51	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	52	#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
e2211743 WD	53
e2211743 WD	54	#undef CONFIG_WATCHDOG /* watchdog disabled */
c837dcb1	55	#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
e2211743	56
c837dcb1	57	#undef CONFIG_UCODE_PATCH
e2211743 WD	58
e2211743 WD	59	/* enable I2C and select the hardware/software driver */
ea818dbb HS	60	#define CONFIG_SYS_I2C
	61	#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
	62	#define CONFIG_SYS_I2C_SOFT_SPEED 50000
	63	#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
e2211743 WD	64	/*
	65	* Software (bit-bang) I2C driver configuration
	66	*/
	67	#define PB_SCL 0x00000020 /* PB 26 */
	68	#define PB_SDA 0x00000010 /* PB 27 */
	69
	70	#define I2C_INIT (immr->im_cpm.cp_pbdir \|= PB_SCL)
	71	#define I2C_ACTIVE (immr->im_cpm.cp_pbdir \|= PB_SDA)
	72	#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
	73	#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
	74	#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SDA; \
c837dcb1	75	else immr->im_cpm.cp_pbdat &= ~PB_SDA
e2211743	76	#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SCL; \
c837dcb1	77	else immr->im_cpm.cp_pbdat &= ~PB_SCL
e2211743 WD	78	#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
e2211743 WD	79
6d0f6bcf JCPV	80	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C04 */
6d0f6bcf JCPV	81	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
c837dcb1	82	/* mask of address bits that overflow into the "EEPROM chip address" */
6d0f6bcf JCPV	83	#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
	84	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	85	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
c837dcb1 WD	86
	87	#define LCD_VIDEO_ADDR (SDRAM_MAX_SIZE-SDRAM_RES_SIZE)
	88	#define LCD_VIDEO_SIZE SDRAM_RES_SIZE /* 2MB */
	89	#define LCD_VIDEO_COLS 640
	90	#define LCD_VIDEO_ROWS 480
	91	#define LCD_VIDEO_FG 255
	92	#define LCD_VIDEO_BG 0
	93
	94	#undef CONFIG_VIDEO /* test only ! s.a devices.c and 8xx */
	95	#define CONFIG_CFB_CONSOLE /* framebuffer console with std input */
e2211743 WD	96	#define CONFIG_VIDEO_LOGO
e2211743 WD	97
c837dcb1 WD	98	#define VIDEO_KBD_INIT_FCT 0 /* no KBD dev on MHPC - use serial */
	99	#define VIDEO_TSTC_FCT serial_tstc
	100	#define VIDEO_GETC_FCT serial_getc
e2211743	101
c837dcb1	102	#define CONFIG_BR0_WORKAROUND 1
e2211743	103
e2211743	104
8353e139 JL	105	/*
	106	* Command line configuration.
	107	*/
	108	#include <config_cmd_default.h>
e2211743	109
8353e139 JL	110	#define CONFIG_CMD_DATE
	111	#define CONFIG_CMD_EEPROM
	112	#define CONFIG_CMD_ELF
	113	#define CONFIG_CMD_I2C
	114	#define CONFIG_CMD_JFFS2
	115	#define CONFIG_CMD_REGINFO
	116
	117
7be044e4 JL	118	/*
	119	* BOOTP options
	120	*/
	121	#define CONFIG_BOOTP_SUBNETMASK
	122	#define CONFIG_BOOTP_GATEWAY
	123	#define CONFIG_BOOTP_HOSTNAME
	124	#define CONFIG_BOOTP_BOOTPATH
	125	#define CONFIG_BOOTP_BOOTFILESIZE
	126
e2211743 WD	127
	128	/*
	129	* Miscellaneous configurable options
	130	*/
6d0f6bcf JCPV	131	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	132	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
8353e139	133	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	134	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
e2211743	135	#else
6d0f6bcf	136	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
e2211743	137	#endif
6d0f6bcf JCPV	138	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	139	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	140	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
e2211743	141
6d0f6bcf JCPV	142	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	143	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
e2211743	144
6d0f6bcf	145	#define CONFIG_SYS_LOAD_ADDR 0x300000 /* default load address */
e2211743	146
6d0f6bcf	147	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
e2211743	148
e2211743 WD	149	/*
	150	* Low Level Configuration Settings
	151	* (address mappings, register initial values, etc.)
	152	* You should know what you are doing if you make changes here.
	153	*/
	154
	155	/*-----------------------------------------------------------------------
	156	* Physical memory map
	157	*/
6d0f6bcf	158	#define CONFIG_SYS_IMMR 0xFFF00000 /* Internal Memory Mapped Register*/
e2211743 WD	159
	160	/*-----------------------------------------------------------------------
	161	* Definitions for initial stack pointer and data area (in DPRAM)
	162	*/
6d0f6bcf	163	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	164	#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
25ddd1fb	165	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	166	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
e2211743 WD	167
	168	/*-----------------------------------------------------------------------
	169	* Start addresses for the final memory configuration
	170	* (Set up by the startup code)
6d0f6bcf	171	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
e2211743	172	*/
6d0f6bcf JCPV	173	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	174	#define CONFIG_SYS_FLASH_BASE 0xfe000000
e2211743	175
6d0f6bcf JCPV	176	#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */
	177	#undef CONFIG_SYS_MONITOR_BASE /* to run U-Boot from RAM */
	178	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	179	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
e2211743	180
700a0c64 WD	181	/*
	182	* JFFS2 partitions
	183	*
	184	*/
	185	/* No command line, one static partition, whole device */
68d7d651	186	#undef CONFIG_CMD_MTDPARTS
700a0c64 WD	187	#define CONFIG_JFFS2_DEV "nor0"
	188	#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
	189	#define CONFIG_JFFS2_PART_OFFSET 0x00000000
	190
	191	/* mtdparts command line support */
	192	/* Note: fake mtd_id used, no linux mtd map file */
	193	/*
68d7d651	194	#define CONFIG_CMD_MTDPARTS
700a0c64 WD	195	#define MTDIDS_DEFAULT "nor0=mhpc-0"
	196	#define MTDPARTS_DEFAULT "mtdparts=mhpc-0:-(jffs2)"
	197	*/
e2211743 WD	198
	199	/*
	200	* For booting Linux, the board info and command line data
	201	* have to be in the first 8 MB of memory, since this is
	202	* the maximum mapped by the Linux kernel during initialization.
	203	*/
6d0f6bcf	204	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map- for Linux */
e2211743 WD	205
	206	/*-----------------------------------------------------------------------
	207	* FLASH organization
	208	*/
6d0f6bcf JCPV	209	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	210	#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
e2211743	211
6d0f6bcf JCPV	212	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	213	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
5a1aceb0	214	#define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf	215	#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN /* Offset of Environment */
0e8d1586	216	#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment */
e2211743 WD	217
	218	/*-----------------------------------------------------------------------
	219	* Cache Configuration
	220	*/
6d0f6bcf	221	#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
8353e139	222	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	223	#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
e2211743 WD	224	#endif
	225
	226	/*-----------------------------------------------------------------------
	227	* SYPCR - System Protection Control 11-9
	228	* SYPCR can only be written once after reset!
	229	*-----------------------------------------------------------------------
	230	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	231	*/
	232	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	233	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
e2211743 WD	234	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
e2211743 WD	235	#else
6d0f6bcf	236	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
8bde7f77	237	SYPCR_SWP)
e2211743 WD	238	#endif
	239
	240	/*-----------------------------------------------------------------------
	241	* SIUMCR - SIU Module Configuration 11-6
	242	*-----------------------------------------------------------------------
	243	* PCMCIA config., multi-function pin tri-state
	244	*/
6d0f6bcf	245	#define CONFIG_SYS_SIUMCR (SIUMCR_SEME)
e2211743 WD	246
	247	/*-----------------------------------------------------------------------
	248	* TBSCR - Time Base Status and Control 11-26
	249	*-----------------------------------------------------------------------
	250	* Clear Reference Interrupt Status, Timebase freezing enabled
	251	*/
6d0f6bcf	252	#define CONFIG_SYS_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBE)
e2211743 WD	253
	254	/*-----------------------------------------------------------------------
	255	* PISCR - Periodic Interrupt Status and Control 11-31
	256	*-----------------------------------------------------------------------
	257	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	258	*/
6d0f6bcf	259	#define CONFIG_SYS_PISCR (PISCR_PS \| PISCR_PITF \| PISCR_PTE)
e2211743 WD	260
	261	/*-----------------------------------------------------------------------
	262	* RTCSC - Real-Time Clock Status and Control Register 12-18
	263	*-----------------------------------------------------------------------
	264	*/
6d0f6bcf	265	#define CONFIG_SYS_RTCSC (RTCSC_SEC \| RTCSC_ALR \| RTCSC_RTF\| RTCSC_RTE)
e2211743 WD	266
	267	/*-----------------------------------------------------------------------
	268	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	269	*-----------------------------------------------------------------------
	270	* Reset PLL lock status sticky bit, timer expired status bit and timer
	271	* interrupt status bit - leave PLL multiplication factor unchanged !
	272	*/
	273	#define MPC8XX_SPEED 50000000L
c837dcb1	274	#define MPC8XX_XIN 5000000L /* ref clk */
e2211743	275	#define MPC8XX_FACT (MPC8XX_SPEED/MPC8XX_XIN)
6d0f6bcf	276	#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) \| \
8bde7f77	277	PLPRCR_SPLSS \| PLPRCR_TEXPS \| PLPRCR_TMIST)
e2211743 WD	278
	279	/*-----------------------------------------------------------------------
	280	* SCCR - System Clock and reset Control Register 15-27
	281	*-----------------------------------------------------------------------
	282	* Set clock output, timebase and RTC source and divider,
	283	* power management and some other internal clocks
	284	*/
	285
	286	#define SCCR_MASK (SCCR_RTDIV \| SCCR_RTSEL) /* SCCR_EBDF11 */
6d0f6bcf	287	#define CONFIG_SYS_SCCR (SCCR_TBS \| SCCR_DFLCD001)
e2211743 WD	288
	289
	290	/*-----------------------------------------------------------------------
	291	* MAMR settings for SDRAM - 16-14
	292	* => 0xC080200F
	293	*-----------------------------------------------------------------------
	294	* periodic timer for refresh
	295	*/
6d0f6bcf JCPV	296	#define CONFIG_SYS_MAMR_PTA 0xC0
6d0f6bcf JCPV	297	#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| MAMR_G0CLA_A11 \| MAMR_TLFA_MSK)
e2211743 WD	298
	299	/*
	300	* BR0 and OR0 (FLASH) used to re-map FLASH
	301	*/
	302
	303	/* allow for max 8 MB of Flash */
	304	#define FLASH_BASE 0xFE000000 /* FLASH bank #0*/
	305	#define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0*/
6d0f6bcf JCPV	306	#define CONFIG_SYS_REMAP_OR_AM 0xFF800000 /* OR addr mask */
6d0f6bcf JCPV	307	#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
e2211743	308
6d0f6bcf	309	#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM \| OR_BI \| OR_SCY_8_CLK) /* (OR_CSNT_SAM \| OR_ACS_DIV2 \| OR_BI \| OR_SCY_6_CLK)*/
e2211743	310
6d0f6bcf JCPV	311	#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	312	#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	313	#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE & BR_BA_MSK) \| BR_PS_16 \| BR_MS_GPCM \| BR_V )
e2211743 WD	314
	315	/*
	316	* BR1 and OR1 (SDRAM)
	317	*/
	318	#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
c837dcb1 WD	319	#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */
c837dcb1 WD	320	#define SDRAM_RES_SIZE 0x00200000 /* 2 MB for framebuffer */
e2211743 WD	321
e2211743 WD	322	/* SDRAM timing: drive GPL5 high on first cycle */
6d0f6bcf	323	#define CONFIG_SYS_OR_TIMING_SDRAM (OR_G5LS)
e2211743	324
6d0f6bcf JCPV	325	#define CONFIG_SYS_OR1_PRELIM ((~(SDRAM_MAX_SIZE)+1)\| CONFIG_SYS_OR_TIMING_SDRAM )
6d0f6bcf JCPV	326	#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
e2211743 WD	327
	328	/*
	329	* BR2/OR2 - DIMM
	330	*/
6d0f6bcf JCPV	331	#define CONFIG_SYS_OR2 (OR_ACS_DIV4)
6d0f6bcf JCPV	332	#define CONFIG_SYS_BR2 (BR_MS_UPMA)
e2211743 WD	333
	334	/*
	335	* BR3/OR3 - DIMM
	336	*/
6d0f6bcf JCPV	337	#define CONFIG_SYS_OR3 (OR_ACS_DIV4)
6d0f6bcf JCPV	338	#define CONFIG_SYS_BR3 (BR_MS_UPMA)
e2211743 WD	339
	340	/*
	341	* BR4/OR4
	342	*/
6d0f6bcf JCPV	343	#define CONFIG_SYS_OR4 0
6d0f6bcf JCPV	344	#define CONFIG_SYS_BR4 0
e2211743 WD	345
	346	/*
	347	* BR5/OR5
	348	*/
6d0f6bcf JCPV	349	#define CONFIG_SYS_OR5 0
6d0f6bcf JCPV	350	#define CONFIG_SYS_BR5 0
e2211743 WD	351
	352	/*
	353	* BR6/OR6
	354	*/
6d0f6bcf JCPV	355	#define CONFIG_SYS_OR6 0
6d0f6bcf JCPV	356	#define CONFIG_SYS_BR6 0
e2211743 WD	357
	358	/*
	359	* BR7/OR7
	360	*/
6d0f6bcf JCPV	361	#define CONFIG_SYS_OR7 0
6d0f6bcf JCPV	362	#define CONFIG_SYS_BR7 0
e2211743 WD	363
	364
	365	/*-----------------------------------------------------------------------
	366	* Debug Entry Mode
	367	*-----------------------------------------------------------------------
	368	*
	369	*/
6d0f6bcf	370	#define CONFIG_SYS_DER 0
e2211743	371
e2211743	372	#endif /* __CONFIG_H */