[J-u-boot.git] / include / configs / M5253EVBE.h

/*
 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 * Hayden Fraser (Hayden.Fraser@freescale.com)
 *
 * SPDX-License-Identifier:	GPL-2.0+ 
 */

#ifndef _M5253EVBE_H
#define _M5253EVBE_H

#define CONFIG_MCF52x2		/* define processor family */
#define CONFIG_M5253		/* define processor type */
#define CONFIG_M5253EVBE	/* define board type */

#define CONFIG_MCFTMR

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)
#define CONFIG_BAUDRATE		115200

#undef CONFIG_WATCHDOG		/* disable watchdog */

#define CONFIG_BOOTDELAY	5

/* Configuration for environment
 * Environment is embedded in u-boot in the second sector of the flash
 */
#ifndef CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_ENV_OFFSET		0x4000
#define CONFIG_ENV_SECT_SIZE	0x2000
#define CONFIG_ENV_IS_IN_FLASH	1
#else
#define CONFIG_ENV_ADDR		0xffe04000
#define CONFIG_ENV_SECT_SIZE	0x2000
#define CONFIG_ENV_IS_IN_FLASH	1
#endif

/*
 * BOOTP options
 */
#undef CONFIG_BOOTP_BOOTFILESIZE
#undef CONFIG_BOOTP_BOOTPATH
#undef CONFIG_BOOTP_GATEWAY
#undef CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>
#define CONFIG_CMD_CACHE
#undef CONFIG_CMD_NET
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_IDE
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC

/* ATA */
#define CONFIG_DOS_PARTITION
#define CONFIG_MAC_PARTITION
#define CONFIG_IDE_RESET	1
#define CONFIG_IDE_PREINIT	1
#define CONFIG_ATAPI
#undef CONFIG_LBA48

#define CONFIG_SYS_IDE_MAXBUS		1
#define CONFIG_SYS_IDE_MAXDEVICE	2

#define CONFIG_SYS_ATA_BASE_ADDR	(CONFIG_SYS_MBAR2 + 0x800)
#define CONFIG_SYS_ATA_IDE0_OFFSET	0

#define CONFIG_SYS_ATA_DATA_OFFSET	0xA0	/* Offset for data I/O */
#define CONFIG_SYS_ATA_REG_OFFSET	0xA0	/* Offset for normal register accesses */
#define CONFIG_SYS_ATA_ALT_OFFSET	0xC0	/* Offset for alternate registers */
#define CONFIG_SYS_ATA_STRIDE		4	/* Interval between registers */

#define CONFIG_SYS_PROMPT		"=> "
#define CONFIG_SYS_LONGHELP		/* undef to save memory */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */

#define CONFIG_SYS_LOAD_ADDR		0x00100000

#define CONFIG_SYS_MEMTEST_START	0x400
#define CONFIG_SYS_MEMTEST_END		0x380000

#define CONFIG_SYS_HZ			1000

#undef CONFIG_SYS_PLL_BYPASS		/* bypass PLL for test purpose */
#define CONFIG_SYS_FAST_CLK
#ifdef CONFIG_SYS_FAST_CLK
#	define CONFIG_SYS_PLLCR	0x1243E054
#	define CONFIG_SYS_CLK		140000000
#else
#	define CONFIG_SYS_PLLCR	0x135a4140
#	define CONFIG_SYS_CLK		70000000
#endif

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

#define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */
#define CONFIG_SYS_MBAR2		0x80000000	/* Module Base Addrs 2 */

/*
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
#define CONFIG_SYS_INIT_RAM_SIZE	0x10000	/* Size of used area in internal SRAM */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_SDRAM_SIZE		8	/* SDRAM size in MB */

#ifdef CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_SYS_MONITOR_BASE	0x20000
#else
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#endif

#define CONFIG_SYS_MONITOR_LEN		0x40000
#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
#define CONFIG_SYS_BOOTPARAMS_LEN	(64*1024)

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)

/* FLASH organization */
#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT	35	/* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT	1000

#define CONFIG_SYS_FLASH_CFI		1
#define CONFIG_FLASH_CFI_DRIVER	1
#define CONFIG_SYS_FLASH_SIZE		0x200000
#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT

/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_DCM)
#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_FLASH_BASE | \
					 CF_ADDRMASK(2) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ACR1		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CEIB | \
					 CF_CACR_DBWE)

/* Port configuration */
#define CONFIG_SYS_FECI2C		0xF0

#define CONFIG_SYS_CS0_BASE		0xFFE00000
#define CONFIG_SYS_CS0_MASK		0x001F0021
#define CONFIG_SYS_CS0_CTRL		0x00001D80

/*-----------------------------------------------------------------------
 * Port configuration
 */
#define CONFIG_SYS_GPIO_FUNC		0x00000008	/* Set gpio pins: none */
#define CONFIG_SYS_GPIO1_FUNC		0x00df00f0	/* 36-39(SWITCH),48-52(FPGAs),54 */
#define CONFIG_SYS_GPIO_EN		0x00000008	/* Set gpio output enable */
#define CONFIG_SYS_GPIO1_EN		0x00c70000	/* Set gpio output enable */
#define CONFIG_SYS_GPIO_OUT		0x00000008	/* Set outputs to default state */
#define CONFIG_SYS_GPIO1_OUT		0x00c70000	/* Set outputs to default state */
#define CONFIG_SYS_GPIO1_LED		0x00400000	/* user led */

#endif				/* _M5253EVB_H */
Commit	Line	Data
a1436a84 TL	1	/*
	2	* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
	3	* Hayden Fraser (Hayden.Fraser@freescale.com)
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
a1436a84 TL	6	*/
	7
	8	#ifndef _M5253EVBE_H
	9	#define _M5253EVBE_H
	10
	11	#define CONFIG_MCF52x2 /* define processor family */
	12	#define CONFIG_M5253 /* define processor type */
	13	#define CONFIG_M5253EVBE /* define board type */
	14
	15	#define CONFIG_MCFTMR
	16
	17	#define CONFIG_MCFUART
6d0f6bcf	18	#define CONFIG_SYS_UART_PORT (0)
80ba61fd	19	#define CONFIG_BAUDRATE 115200
a1436a84 TL	20
	21	#undef CONFIG_WATCHDOG /* disable watchdog */
	22
	23	#define CONFIG_BOOTDELAY 5
	24
	25	/* Configuration for environment
	26	* Environment is embedded in u-boot in the second sector of the flash
	27	*/
	28	#ifndef CONFIG_MONITOR_IS_IN_RAM
0e8d1586 JCPV	29	#define CONFIG_ENV_OFFSET 0x4000
0e8d1586 JCPV	30	#define CONFIG_ENV_SECT_SIZE 0x2000
5a1aceb0	31	#define CONFIG_ENV_IS_IN_FLASH 1
a1436a84	32	#else
0e8d1586 JCPV	33	#define CONFIG_ENV_ADDR 0xffe04000
0e8d1586 JCPV	34	#define CONFIG_ENV_SECT_SIZE 0x2000
5a1aceb0	35	#define CONFIG_ENV_IS_IN_FLASH 1
a1436a84 TL	36	#endif
	37
	38	/*
	39	* BOOTP options
	40	*/
	41	#undef CONFIG_BOOTP_BOOTFILESIZE
	42	#undef CONFIG_BOOTP_BOOTPATH
	43	#undef CONFIG_BOOTP_GATEWAY
	44	#undef CONFIG_BOOTP_HOSTNAME
	45
	46	/*
	47	* Command line configuration.
	48	*/
	49	#include <config_cmd_default.h>
dd9f054e	50	#define CONFIG_CMD_CACHE
a1436a84 TL	51	#undef CONFIG_CMD_NET
	52	#define CONFIG_CMD_LOADB
	53	#define CONFIG_CMD_LOADS
	54	#define CONFIG_CMD_EXT2
	55	#define CONFIG_CMD_FAT
	56	#define CONFIG_CMD_IDE
	57	#define CONFIG_CMD_MEMORY
	58	#define CONFIG_CMD_MISC
	59
	60	/* ATA */
	61	#define CONFIG_DOS_PARTITION
	62	#define CONFIG_MAC_PARTITION
	63	#define CONFIG_IDE_RESET 1
	64	#define CONFIG_IDE_PREINIT 1
	65	#define CONFIG_ATAPI
	66	#undef CONFIG_LBA48
	67
6d0f6bcf JCPV	68	#define CONFIG_SYS_IDE_MAXBUS 1
6d0f6bcf JCPV	69	#define CONFIG_SYS_IDE_MAXDEVICE 2
a1436a84	70
6d0f6bcf JCPV	71	#define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)
6d0f6bcf JCPV	72	#define CONFIG_SYS_ATA_IDE0_OFFSET 0
a1436a84	73
6d0f6bcf JCPV	74	#define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
	75	#define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
	76	#define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
	77	#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
a1436a84	78
6d0f6bcf JCPV	79	#define CONFIG_SYS_PROMPT "=> "
6d0f6bcf JCPV	80	#define CONFIG_SYS_LONGHELP /* undef to save memory */
a1436a84 TL	81
a1436a84 TL	82	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	83	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
a1436a84	84	#else
6d0f6bcf	85	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
a1436a84	86	#endif
6d0f6bcf JCPV	87	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	88	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	89	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
a1436a84	90
6d0f6bcf	91	#define CONFIG_SYS_LOAD_ADDR 0x00100000
a1436a84	92
6d0f6bcf JCPV	93	#define CONFIG_SYS_MEMTEST_START 0x400
6d0f6bcf JCPV	94	#define CONFIG_SYS_MEMTEST_END 0x380000
a1436a84	95
6d0f6bcf	96	#define CONFIG_SYS_HZ 1000
a1436a84	97
6d0f6bcf JCPV	98	#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
	99	#define CONFIG_SYS_FAST_CLK
	100	#ifdef CONFIG_SYS_FAST_CLK
	101	# define CONFIG_SYS_PLLCR 0x1243E054
	102	# define CONFIG_SYS_CLK 140000000
a1436a84	103	#else
6d0f6bcf JCPV	104	# define CONFIG_SYS_PLLCR 0x135a4140
6d0f6bcf JCPV	105	# define CONFIG_SYS_CLK 70000000
a1436a84 TL	106	#endif
	107
	108	/*
	109	* Low Level Configuration Settings
	110	* (address mappings, register initial values, etc.)
	111	* You should know what you are doing if you make changes here.
	112	*/
	113
6d0f6bcf JCPV	114	#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
6d0f6bcf JCPV	115	#define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
a1436a84 TL	116
	117	/*
	118	* Definitions for initial stack pointer and data area (in DPRAM)
	119	*/
6d0f6bcf	120	#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
553f0982	121	#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
25ddd1fb	122	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	123	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
a1436a84 TL	124
	125	/*
	126	* Start addresses for the final memory configuration
	127	* (Set up by the startup code)
6d0f6bcf	128	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
a1436a84	129	*/
6d0f6bcf JCPV	130	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	131	#define CONFIG_SYS_SDRAM_SIZE 8 /* SDRAM size in MB */
a1436a84 TL	132
a1436a84 TL	133	#ifdef CONFIG_MONITOR_IS_IN_RAM
6d0f6bcf	134	#define CONFIG_SYS_MONITOR_BASE 0x20000
a1436a84	135	#else
6d0f6bcf	136	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
a1436a84 TL	137	#endif
a1436a84 TL	138
6d0f6bcf JCPV	139	#define CONFIG_SYS_MONITOR_LEN 0x40000
	140	#define CONFIG_SYS_MALLOC_LEN (256 << 10)
	141	#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
a1436a84 TL	142
	143	/*
	144	* For booting Linux, the board info and command line data
	145	* have to be in the first 8 MB of memory, since this is
	146	* the maximum mapped by the Linux kernel during initialization ??
	147	*/
6d0f6bcf	148	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
d6e4baf4	149	#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
a1436a84 TL	150
a1436a84 TL	151	/* FLASH organization */
012522fe	152	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
6d0f6bcf JCPV	153	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	154	#define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */
	155	#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
a1436a84	156
6d0f6bcf	157	#define CONFIG_SYS_FLASH_CFI 1
00b1883a	158	#define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf JCPV	159	#define CONFIG_SYS_FLASH_SIZE 0x200000
6d0f6bcf JCPV	160	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
a1436a84 TL	161
a1436a84 TL	162	/* Cache Configuration */
6d0f6bcf	163	#define CONFIG_SYS_CACHELINE_SIZE 16
a1436a84	164
dd9f054e	165	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	166	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	167	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	168	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	169	#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
	170	#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE \| \
	171	CF_ADDRMASK(2) \| \
	172	CF_ACR_EN \| CF_ACR_SM_ALL)
	173	#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE \| \
	174	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	175	CF_ACR_EN \| CF_ACR_SM_ALL)
	176	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB \| CF_CACR_CEIB \| \
	177	CF_CACR_DBWE)
	178
a1436a84	179	/* Port configuration */
6d0f6bcf	180	#define CONFIG_SYS_FECI2C 0xF0
a1436a84	181
012522fe TL	182	#define CONFIG_SYS_CS0_BASE 0xFFE00000
	183	#define CONFIG_SYS_CS0_MASK 0x001F0021
	184	#define CONFIG_SYS_CS0_CTRL 0x00001D80
a1436a84 TL	185
	186	/*-----------------------------------------------------------------------
	187	* Port configuration
	188	*/
6d0f6bcf JCPV	189	#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
	190	#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
	191	#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
	192	#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
	193	#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
	194	#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
	195	#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
a1436a84 TL	196
a1436a84 TL	197	#endif /* _M5253EVB_H */