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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
ae440ab0 | 2 | /* |
a62c6061 | 3 | * Copyright (C) 2016-2018 Toradex AG |
ae440ab0 SA |
4 | */ |
5 | ||
9b4a205f | 6 | #include <common.h> |
9a3b4ceb | 7 | #include <cpu_func.h> |
9b4a205f | 8 | #include <init.h> |
90526e9f | 9 | #include <net.h> |
ae440ab0 SA |
10 | #include <asm/arch/clock.h> |
11 | #include <asm/arch/crm_regs.h> | |
12 | #include <asm/arch/imx-regs.h> | |
13 | #include <asm/arch/mx7-pins.h> | |
14 | #include <asm/arch/sys_proto.h> | |
401d1c4f | 15 | #include <asm/global_data.h> |
ae440ab0 | 16 | #include <asm/gpio.h> |
552a848e | 17 | #include <asm/mach-imx/iomux-v3.h> |
ae440ab0 | 18 | #include <asm/io.h> |
ae440ab0 SA |
19 | #include <dm.h> |
20 | #include <dm/platform_data/serial_mxc.h> | |
64095704 | 21 | #include <fdt_support.h> |
e37ac717 | 22 | #include <fsl_esdhc_imx.h> |
64095704 | 23 | #include <jffs2/load_kernel.h> |
c05ed00a | 24 | #include <linux/delay.h> |
ae440ab0 SA |
25 | #include <linux/sizes.h> |
26 | #include <mmc.h> | |
27 | #include <miiphy.h> | |
64095704 | 28 | #include <mtd_node.h> |
ae440ab0 | 29 | #include <netdev.h> |
02ad90ec SA |
30 | #include <power/pmic.h> |
31 | #include <power/rn5t567_pmic.h> | |
5a986dfe | 32 | #include <usb.h> |
ae440ab0 | 33 | #include <usb/ehci-ci.h> |
37fa4125 | 34 | #include "../common/tdx-common.h" |
ae440ab0 SA |
35 | |
36 | DECLARE_GLOBAL_DATA_PTR; | |
37 | ||
38 | #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ | |
39 | PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) | |
40 | ||
ae440ab0 SA |
41 | #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) |
42 | #define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM) | |
43 | ||
44 | #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) | |
45 | ||
ae440ab0 SA |
46 | #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \ |
47 | PAD_CTL_DSE_3P3V_49OHM) | |
48 | ||
49 | #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) | |
50 | ||
51 | #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM) | |
52 | ||
5a986dfe SA |
53 | #define USB_CDET_GPIO IMX_GPIO_NR(7, 14) |
54 | ||
0c39564d HDF |
55 | #define FLASH_DETECTION_CTRL (PAD_CTL_HYS | PAD_CTL_PUE) |
56 | #define FLASH_DET_GPIO IMX_GPIO_NR(6, 11) | |
57 | ||
58 | static bool is_emmc; | |
59 | ||
ae440ab0 SA |
60 | int dram_init(void) |
61 | { | |
787075e0 | 62 | gd->ram_size = get_ram_size((void *)PHYS_SDRAM, imx_ddr_size()); |
ae440ab0 SA |
63 | |
64 | return 0; | |
65 | } | |
66 | ||
0c39564d | 67 | static iomux_v3_cfg_t const flash_detection_pads[] = { |
29e31c54 | 68 | MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(FLASH_DETECTION_CTRL) | MUX_MODE_SION, |
0c39564d HDF |
69 | }; |
70 | ||
ae440ab0 SA |
71 | static iomux_v3_cfg_t const uart1_pads[] = { |
72 | MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), | |
73 | MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), | |
74 | MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL), | |
75 | MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL), | |
76 | }; | |
77 | ||
5a986dfe SA |
78 | #ifdef CONFIG_USB_EHCI_MX7 |
79 | static iomux_v3_cfg_t const usb_cdet_pads[] = { | |
80 | MX7D_PAD_ENET1_CRS__GPIO7_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
81 | }; | |
82 | #endif | |
83 | ||
a62c6061 | 84 | #ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND |
ae440ab0 SA |
85 | static iomux_v3_cfg_t const gpmi_pads[] = { |
86 | MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), | |
87 | MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), | |
88 | MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), | |
89 | MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), | |
90 | MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), | |
91 | MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), | |
92 | MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), | |
93 | MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), | |
94 | MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), | |
95 | MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), | |
96 | MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), | |
97 | MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), | |
98 | MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL), | |
99 | MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), | |
100 | MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL), | |
101 | }; | |
102 | ||
103 | static void setup_gpmi_nand(void) | |
104 | { | |
105 | imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); | |
106 | ||
107 | /* NAND_USDHC_BUS_CLK is set in rom */ | |
108 | set_clk_nand(); | |
109 | } | |
110 | #endif | |
111 | ||
b86986c7 | 112 | #ifdef CONFIG_VIDEO |
ae440ab0 SA |
113 | static iomux_v3_cfg_t const backlight_pads[] = { |
114 | /* Backlight On */ | |
115 | MX7D_PAD_SD1_WP__GPIO5_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
116 | /* Backlight PWM<A> (multiplexed pin) */ | |
117 | MX7D_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
118 | MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
119 | }; | |
120 | ||
121 | #define GPIO_BL_ON IMX_GPIO_NR(5, 1) | |
122 | #define GPIO_PWM_A IMX_GPIO_NR(1, 8) | |
123 | ||
124 | static int setup_lcd(void) | |
125 | { | |
ae440ab0 SA |
126 | imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads)); |
127 | ||
128 | /* Set BL_ON */ | |
129 | gpio_request(GPIO_BL_ON, "BL_ON"); | |
130 | gpio_direction_output(GPIO_BL_ON, 1); | |
131 | ||
132 | /* Set PWM<A> to full brightness (assuming inversed polarity) */ | |
133 | gpio_request(GPIO_PWM_A, "PWM<A>"); | |
134 | gpio_direction_output(GPIO_PWM_A, 0); | |
135 | ||
136 | return 0; | |
137 | } | |
138 | #endif | |
139 | ||
a3c90217 GS |
140 | /* |
141 | * Backlight off before OS handover | |
142 | */ | |
143 | void board_preboot_os(void) | |
144 | { | |
b86986c7 | 145 | #ifdef CONFIG_VIDEO |
a3c90217 GS |
146 | gpio_direction_output(GPIO_PWM_A, 1); |
147 | gpio_direction_output(GPIO_BL_ON, 0); | |
b4c9cd68 | 148 | #endif |
a3c90217 GS |
149 | } |
150 | ||
ae440ab0 SA |
151 | static void setup_iomux_uart(void) |
152 | { | |
153 | imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); | |
154 | } | |
155 | ||
ae440ab0 | 156 | #ifdef CONFIG_FEC_MXC |
ae440ab0 SA |
157 | static int setup_fec(void) |
158 | { | |
159 | struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs | |
160 | = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; | |
161 | ||
162 | #ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK | |
163 | /* | |
164 | * Use 50M anatop REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17] | |
165 | * and output it on the pin | |
166 | */ | |
167 | clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], | |
168 | IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK, | |
169 | IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK); | |
170 | #else | |
171 | /* Use 50M external CLK for ENET1, set gpr1[13], clear gpr1[17] */ | |
172 | clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], | |
173 | IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK, | |
174 | IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK); | |
175 | #endif | |
176 | ||
8590786a | 177 | return set_clk_enet(ENET_50MHZ); |
ae440ab0 SA |
178 | } |
179 | ||
ae440ab0 SA |
180 | #endif |
181 | ||
182 | int board_early_init_f(void) | |
183 | { | |
184 | setup_iomux_uart(); | |
185 | ||
ae440ab0 SA |
186 | return 0; |
187 | } | |
188 | ||
189 | int board_init(void) | |
190 | { | |
191 | /* address of boot parameters */ | |
192 | gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; | |
193 | ||
0c39564d | 194 | /* |
29e31c54 | 195 | * Enable GPIO SION on NAND_WE_B/eMMC_RST with 100k pull-down. eMMC_RST |
0c39564d | 196 | * is pulled high with 4.7k for eMMC devices. This allows to reliably |
29e31c54 | 197 | * detect eMMC vs NAND flash. |
0c39564d HDF |
198 | */ |
199 | imx_iomux_v3_setup_multiple_pads(flash_detection_pads, ARRAY_SIZE(flash_detection_pads)); | |
200 | gpio_request(FLASH_DET_GPIO, "flash-detection-gpio"); | |
201 | is_emmc = gpio_get_value(FLASH_DET_GPIO); | |
202 | gpio_free(FLASH_DET_GPIO); | |
203 | ||
ae440ab0 SA |
204 | #ifdef CONFIG_FEC_MXC |
205 | setup_fec(); | |
206 | #endif | |
207 | ||
a62c6061 | 208 | #ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND |
ae440ab0 SA |
209 | setup_gpmi_nand(); |
210 | #endif | |
211 | ||
5a986dfe SA |
212 | #ifdef CONFIG_USB_EHCI_MX7 |
213 | imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads)); | |
214 | gpio_request(USB_CDET_GPIO, "usb-cdet-gpio"); | |
215 | #endif | |
216 | ||
ae440ab0 SA |
217 | return 0; |
218 | } | |
219 | ||
02ad90ec SA |
220 | #ifdef CONFIG_DM_PMIC |
221 | int power_init_board(void) | |
222 | { | |
223 | struct udevice *dev; | |
224 | int reg, ver; | |
225 | int ret; | |
226 | ||
227 | ||
25ab9798 | 228 | ret = pmic_get("pmic@33", &dev); |
02ad90ec SA |
229 | if (ret) |
230 | return ret; | |
231 | ver = pmic_reg_read(dev, RN5T567_LSIVER); | |
232 | reg = pmic_reg_read(dev, RN5T567_OTPVER); | |
233 | ||
234 | printf("PMIC: RN5T567 LSIVER=0x%02x OTPVER=0x%02x\n", ver, reg); | |
235 | ||
236 | /* set judge and press timer of N_OE to minimal values */ | |
237 | pmic_clrsetbits(dev, RN5T567_NOETIMSETCNT, 0x7, 0); | |
238 | ||
05ed964d SA |
239 | /* configure sleep slot for 3.3V Ethernet */ |
240 | reg = pmic_reg_read(dev, RN5T567_LDO1_SLOT); | |
241 | reg = (reg & 0xf0) | reg >> 4; | |
242 | pmic_reg_write(dev, RN5T567_LDO1_SLOT, reg); | |
243 | ||
244 | /* disable DCDC2 discharge to avoid backfeeding through VFB2 */ | |
245 | pmic_clrsetbits(dev, RN5T567_DC2CTL, 0x2, 0); | |
246 | ||
247 | /* configure sleep slot for ARM rail */ | |
248 | reg = pmic_reg_read(dev, RN5T567_DC2_SLOT); | |
249 | reg = (reg & 0xf0) | reg >> 4; | |
250 | pmic_reg_write(dev, RN5T567_DC2_SLOT, reg); | |
251 | ||
252 | /* disable LDO2 discharge to avoid backfeeding from +V3.3_SD */ | |
253 | pmic_clrsetbits(dev, RN5T567_LDODIS1, 0x2, 0); | |
254 | ||
02ad90ec SA |
255 | return 0; |
256 | } | |
257 | ||
35b65dd8 | 258 | void reset_cpu(void) |
02ad90ec SA |
259 | { |
260 | struct udevice *dev; | |
261 | ||
25ab9798 | 262 | pmic_get("pmic@33", &dev); |
02ad90ec SA |
263 | |
264 | /* Use PMIC to reset, set REPWRTIM to 0 and REPWRON to 1 */ | |
265 | pmic_reg_write(dev, RN5T567_REPCNT, 0x1); | |
266 | pmic_reg_write(dev, RN5T567_SLPCNT, 0x1); | |
267 | ||
268 | /* | |
269 | * Re-power factor detection on PMIC side is not instant. 1ms | |
270 | * proved to be enough time until reset takes effect. | |
271 | */ | |
272 | mdelay(1); | |
273 | } | |
274 | #endif | |
275 | ||
37fa4125 | 276 | #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) |
b75d8dc5 | 277 | int ft_board_setup(void *blob, struct bd_info *bd) |
37fa4125 | 278 | { |
c671d8af IO |
279 | #if defined(CONFIG_IMX_BOOTAUX) && defined(CONFIG_ARCH_FIXUP_FDT_MEMORY) |
280 | int up; | |
281 | ||
282 | up = arch_auxiliary_core_check_up(0); | |
283 | if (up) { | |
284 | int ret; | |
285 | int areas = 1; | |
286 | u64 start[2], size[2]; | |
287 | ||
288 | /* | |
289 | * Reserve 1MB of memory for M4 (1MiB is also the minimum | |
290 | * alignment for Linux due to MMU section size restrictions). | |
291 | */ | |
292 | start[0] = gd->bd->bi_dram[0].start; | |
293 | size[0] = SZ_256M - SZ_1M; | |
294 | ||
295 | /* If needed, create a second entry for memory beyond 256M */ | |
296 | if (gd->bd->bi_dram[0].size > SZ_256M) { | |
297 | start[1] = gd->bd->bi_dram[0].start + SZ_256M; | |
298 | size[1] = gd->bd->bi_dram[0].size - SZ_256M; | |
299 | areas = 2; | |
300 | } | |
301 | ||
302 | ret = fdt_set_usable_memory(blob, start, size, areas); | |
303 | if (ret) { | |
304 | eprintf("Cannot set usable memory\n"); | |
305 | return ret; | |
306 | } | |
307 | } else { | |
308 | int off; | |
309 | ||
310 | off = fdt_node_offset_by_compatible(blob, -1, | |
311 | "fsl,imx7d-rpmsg"); | |
312 | if (off > 0) | |
313 | fdt_status_disabled(blob, off); | |
314 | } | |
315 | #endif | |
64095704 | 316 | |
37fa4125 SA |
317 | return ft_common_board_setup(blob, bd); |
318 | } | |
319 | #endif | |
320 | ||
ae440ab0 | 321 | #ifdef CONFIG_USB_EHCI_MX7 |
4625ff65 | 322 | int board_fix_fdt(void *rw_fdt_blob) |
ae440ab0 | 323 | { |
92be5e4f FE |
324 | int ret; |
325 | ||
4625ff65 MZ |
326 | /* i.MX 7Solo has only one single USB OTG1 but no USB host port */ |
327 | if (is_cpu_type(MXC_CPU_MX7S)) { | |
328 | int offset = fdt_path_offset(rw_fdt_blob, "/soc/bus@30800000/usb@30b20000"); | |
5a986dfe | 329 | |
92be5e4f FE |
330 | /* |
331 | * We're changing from status = "okay" to status = "disabled". | |
332 | * In this case we'll need more space, so increase the size | |
333 | * a little bit. | |
334 | */ | |
335 | ret = fdt_increase_size(rw_fdt_blob, 32); | |
336 | if (ret < 0) { | |
337 | printf("Cannot increase FDT size: %d\n", ret); | |
338 | return ret; | |
339 | } | |
340 | ||
4625ff65 | 341 | return fdt_status_disabled(rw_fdt_blob, offset); |
5a986dfe | 342 | } |
4625ff65 MZ |
343 | |
344 | return 0; | |
5a986dfe | 345 | } |
195011b2 | 346 | |
46307ef0 | 347 | #if defined(CONFIG_BOARD_LATE_INIT) |
195011b2 IO |
348 | int board_late_init(void) |
349 | { | |
b86986c7 | 350 | #if defined(CONFIG_VIDEO) |
195011b2 | 351 | setup_lcd(); |
195011b2 | 352 | #endif |
46307ef0 | 353 | |
220bb4e1 | 354 | if (IS_ENABLED(CONFIG_USB) && is_boot_from_usb()) { |
46307ef0 | 355 | env_set("bootdelay", "0"); |
220bb4e1 HDF |
356 | if (IS_ENABLED(CONFIG_CMD_USB_SDP)) { |
357 | printf("Serial Downloader recovery mode, using sdp command\n"); | |
358 | env_set("bootcmd", "sdp 0"); | |
359 | } else if (IS_ENABLED(CONFIG_CMD_FASTBOOT)) { | |
360 | printf("Fastboot recovery mode, using fastboot command\n"); | |
361 | env_set("bootcmd", "fastboot usb 0"); | |
362 | } | |
46307ef0 | 363 | } |
220bb4e1 | 364 | |
0c39564d HDF |
365 | if (is_emmc) |
366 | env_set("variant", "-emmc"); | |
367 | else | |
368 | env_set("variant", ""); | |
369 | ||
195011b2 IO |
370 | return 0; |
371 | } | |
46307ef0 | 372 | #endif /* CONFIG_BOARD_LATE_INIT */ |
195011b2 | 373 | |
4625ff65 | 374 | #endif /* CONFIG_USB_EHCI_MX7 */ |