[J-u-boot.git] / drivers / video / pxa_lcd.c

/*
 * PXA LCD Controller
 *
 * (C) Copyright 2001-2002
 * Wolfgang Denk, DENX Software Engineering -- wd@denx.de
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/************************************************************************/
/* ** HEADER FILES							*/
/************************************************************************/

#include <common.h>
#include <asm/arch/pxa-regs.h>
#include <asm/io.h>
#include <lcd.h>
#include <linux/types.h>
#include <stdarg.h>
#include <stdio_dev.h>

/* #define DEBUG */

#ifdef CONFIG_LCD

/*----------------------------------------------------------------------*/
/*
 * Define panel bpp, LCCR0, LCCR3 and panel_info video struct for
 * your display.
 */

#ifdef CONFIG_PXA_VGA
/* LCD outputs connected to a video DAC  */
# define LCD_BPP	LCD_COLOR8

/* you have to set lccr0 and lccr3 (including pcd) */
# define REG_LCCR0	0x003008f8
# define REG_LCCR3	0x0300FF01

/* 640x480x16 @ 61 Hz */
vidinfo_t panel_info = {
	.vl_col		= 640,
	.vl_row		= 480,
	.vl_width	= 640,
	.vl_height	= 480,
	.vl_clkp	= CONFIG_SYS_HIGH,
	.vl_oep		= CONFIG_SYS_HIGH,
	.vl_hsp		= CONFIG_SYS_HIGH,
	.vl_vsp		= CONFIG_SYS_HIGH,
	.vl_dp		= CONFIG_SYS_HIGH,
	.vl_bpix	= LCD_BPP,
	.vl_lbw		= 0,
	.vl_splt	= 0,
	.vl_clor	= 0,
	.vl_tft		= 1,
	.vl_hpw		= 40,
	.vl_blw		= 56,
	.vl_elw		= 56,
	.vl_vpw		= 20,
	.vl_bfw		= 8,
	.vl_efw		= 8,
};
#endif /* CONFIG_PXA_VIDEO */

/*----------------------------------------------------------------------*/
#ifdef CONFIG_SHARP_LM8V31

# define LCD_BPP	LCD_COLOR8
# define LCD_INVERT_COLORS	/* Needed for colors to be correct, but why?	*/

/* you have to set lccr0 and lccr3 (including pcd) */
# define REG_LCCR0	0x0030087C
# define REG_LCCR3	0x0340FF08

vidinfo_t panel_info = {
	.vl_col		= 640,
	.vl_row		= 480,
	.vl_width	= 157,
	.vl_height	= 118,
	.vl_clkp	= CONFIG_SYS_HIGH,
	.vl_oep		= CONFIG_SYS_HIGH,
	.vl_hsp		= CONFIG_SYS_HIGH,
	.vl_vsp		= CONFIG_SYS_HIGH,
	.vl_dp		= CONFIG_SYS_HIGH,
	.vl_bpix	= LCD_BPP,
	.vl_lbw		= 0,
	.vl_splt	= 1,
	.vl_clor	= 1,
	.vl_tft		= 0,
	.vl_hpw		= 1,
	.vl_blw		= 3,
	.vl_elw		= 3,
	.vl_vpw		= 1,
	.vl_bfw		= 0,
	.vl_efw		= 0,
};
#endif /* CONFIG_SHARP_LM8V31 */
/*----------------------------------------------------------------------*/
#ifdef CONFIG_VOIPAC_LCD

# define LCD_BPP	LCD_COLOR8
# define LCD_INVERT_COLORS

/* you have to set lccr0 and lccr3 (including pcd) */
# define REG_LCCR0	0x043008f8
# define REG_LCCR3	0x0340FF08

vidinfo_t panel_info = {
	.vl_col		= 640,
	.vl_row		= 480,
	.vl_width	= 157,
	.vl_height	= 118,
	.vl_clkp	= CONFIG_SYS_HIGH,
	.vl_oep		= CONFIG_SYS_HIGH,
	.vl_hsp		= CONFIG_SYS_HIGH,
	.vl_vsp		= CONFIG_SYS_HIGH,
	.vl_dp		= CONFIG_SYS_HIGH,
	.vl_bpix	= LCD_BPP,
	.vl_lbw		= 0,
	.vl_splt	= 1,
	.vl_clor	= 1,
	.vl_tft		= 1,
	.vl_hpw		= 32,
	.vl_blw		= 144,
	.vl_elw		= 32,
	.vl_vpw		= 2,
	.vl_bfw		= 13,
	.vl_efw		= 30,
};
#endif /* CONFIG_VOIPAC_LCD */

/*----------------------------------------------------------------------*/
#ifdef CONFIG_HITACHI_SX14
/* Hitachi SX14Q004-ZZA color STN LCD */
#define LCD_BPP		LCD_COLOR8

/* you have to set lccr0 and lccr3 (including pcd) */
#define REG_LCCR0	0x00301079
#define REG_LCCR3	0x0340FF20

vidinfo_t panel_info = {
	.vl_col		= 320,
	.vl_row		= 240,
	.vl_width	= 167,
	.vl_height	= 109,
	.vl_clkp	= CONFIG_SYS_HIGH,
	.vl_oep		= CONFIG_SYS_HIGH,
	.vl_hsp		= CONFIG_SYS_HIGH,
	.vl_vsp		= CONFIG_SYS_HIGH,
	.vl_dp		= CONFIG_SYS_HIGH,
	.vl_bpix	= LCD_BPP,
	.vl_lbw		= 1,
	.vl_splt	= 0,
	.vl_clor	= 1,
	.vl_tft		= 0,
	.vl_hpw		= 1,
	.vl_blw		= 1,
	.vl_elw		= 1,
	.vl_vpw		= 7,
	.vl_bfw		= 0,
	.vl_efw		= 0,
};
#endif /* CONFIG_HITACHI_SX14 */

/*----------------------------------------------------------------------*/
#ifdef CONFIG_LMS283GF05

# define LCD_BPP	LCD_COLOR8
/*# define LCD_INVERT_COLORS*/

/* you have to set lccr0 and lccr3 (including pcd) */
# define REG_LCCR0	0x043008f8
# define REG_LCCR3	0x03b00009

vidinfo_t panel_info = {
	.vl_col		= 240,
	.vl_row		= 320,
	.vl_width	= 240,
	.vl_height	= 320,
	.vl_clkp	= CONFIG_SYS_HIGH,
	.vl_oep		= CONFIG_SYS_LOW,
	.vl_hsp		= CONFIG_SYS_LOW,
	.vl_vsp		= CONFIG_SYS_LOW,
	.vl_dp		= CONFIG_SYS_HIGH,
	.vl_bpix	= LCD_BPP,
	.vl_lbw		= 0,
	.vl_splt	= 1,
	.vl_clor	= 1,
	.vl_tft		= 1,
	.vl_hpw		= 4,
	.vl_blw		= 4,
	.vl_elw		= 8,
	.vl_vpw		= 4,
	.vl_bfw		= 4,
	.vl_efw		= 8,
};
#endif /* CONFIG_LMS283GF05 */

/*----------------------------------------------------------------------*/

#ifdef CONFIG_ACX517AKN

# define LCD_BPP	LCD_COLOR8

/* you have to set lccr0 and lccr3 (including pcd) */
# define REG_LCCR0	0x003008f9
# define REG_LCCR3	0x03700006

vidinfo_t panel_info = {
	.vl_col		= 320,
	.vl_row		= 320,
	.vl_width	= 320,
	.vl_height	= 320,
	.vl_clkp	= CONFIG_SYS_HIGH,
	.vl_oep		= CONFIG_SYS_LOW,
	.vl_hsp		= CONFIG_SYS_LOW,
	.vl_vsp		= CONFIG_SYS_LOW,
	.vl_dp		= CONFIG_SYS_HIGH,
	.vl_bpix	= LCD_BPP,
	.vl_lbw		= 0,
	.vl_splt	= 1,
	.vl_clor	= 1,
	.vl_tft		= 1,
	.vl_hpw		= 0x04,
	.vl_blw		= 0x1c,
	.vl_elw		= 0x08,
	.vl_vpw		= 0x01,
	.vl_bfw		= 0x07,
	.vl_efw		= 0x08,
};
#endif /* CONFIG_ACX517AKN */

#ifdef CONFIG_ACX544AKN

# define LCD_BPP	LCD_COLOR16

/* you have to set lccr0 and lccr3 (including pcd) */
# define REG_LCCR0	0x003008f9
# define REG_LCCR3	0x04700007 /* 16bpp */

vidinfo_t panel_info = {
	.vl_col		= 320,
	.vl_row		= 320,
	.vl_width	= 320,
	.vl_height	= 320,
	.vl_clkp	= CONFIG_SYS_LOW,
	.vl_oep		= CONFIG_SYS_LOW,
	.vl_hsp		= CONFIG_SYS_LOW,
	.vl_vsp		= CONFIG_SYS_LOW,
	.vl_dp		= CONFIG_SYS_LOW,
	.vl_bpix	= LCD_BPP,
	.vl_lbw		= 0,
	.vl_splt	= 0,
	.vl_clor	= 1,
	.vl_tft		= 1,
	.vl_hpw		= 0x05,
	.vl_blw		= 0x13,
	.vl_elw		= 0x08,
	.vl_vpw		= 0x02,
	.vl_bfw		= 0x07,
	.vl_efw		= 0x05,
};
#endif /* CONFIG_ACX544AKN */

/*----------------------------------------------------------------------*/

#ifdef CONFIG_LQ038J7DH53

# define LCD_BPP	LCD_COLOR8

/* you have to set lccr0 and lccr3 (including pcd) */
# define REG_LCCR0	0x003008f9
# define REG_LCCR3	0x03700004

vidinfo_t panel_info = {
	.vl_col		= 320,
	.vl_row		= 480,
	.vl_width	= 320,
	.vl_height	= 480,
	.vl_clkp	= CONFIG_SYS_HIGH,
	.vl_oep		= CONFIG_SYS_LOW,
	.vl_hsp		= CONFIG_SYS_LOW,
	.vl_vsp		= CONFIG_SYS_LOW,
	.vl_dp		= CONFIG_SYS_HIGH,
	.vl_bpix	= LCD_BPP,
	.vl_lbw		= 0,
	.vl_splt	= 1,
	.vl_clor	= 1,
	.vl_tft		= 1,
	.vl_hpw		= 0x04,
	.vl_blw		= 0x20,
	.vl_elw		= 0x01,
	.vl_vpw		= 0x01,
	.vl_bfw		= 0x04,
	.vl_efw		= 0x01,
};
#endif /* CONFIG_ACX517AKN */

/*----------------------------------------------------------------------*/

#ifdef CONFIG_LITTLETON_LCD
# define LCD_BPP	LCD_COLOR8

/* you have to set lccr0 and lccr3 (including pcd) */
# define REG_LCCR0	0x003008f8
# define REG_LCCR3	0x0300FF04

vidinfo_t panel_info = {
	.vl_col		= 480,
	.vl_row		= 640,
	.vl_width	= 480,
	.vl_height	= 640,
	.vl_clkp	= CONFIG_SYS_HIGH,
	.vl_oep		= CONFIG_SYS_HIGH,
	.vl_hsp		= CONFIG_SYS_HIGH,
	.vl_vsp		= CONFIG_SYS_HIGH,
	.vl_dp		= CONFIG_SYS_HIGH,
	.vl_bpix	= LCD_BPP,
	.vl_lbw		= 0,
	.vl_splt	= 0,
	.vl_clor	= 0,
	.vl_tft		= 1,
	.vl_hpw		= 9,
	.vl_blw		= 8,
	.vl_elw		= 24,
	.vl_vpw		= 2,
	.vl_bfw		= 2,
	.vl_efw		= 4,
};
#endif /* CONFIG_LITTLETON_LCD */

/*----------------------------------------------------------------------*/

static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid);
static void pxafb_setup_gpio (vidinfo_t *vid);
static void pxafb_enable_controller (vidinfo_t *vid);
static int pxafb_init (vidinfo_t *vid);

/************************************************************************/
/* ---------------  PXA chipset specific functions  ------------------- */
/************************************************************************/

ushort *configuration_get_cmap(void)
{
	struct pxafb_info *fbi = &panel_info.pxa;
	return (ushort *)fbi->palette;
}

void lcd_ctrl_init (void *lcdbase)
{
	pxafb_init_mem(lcdbase, &panel_info);
	pxafb_init(&panel_info);
	pxafb_setup_gpio(&panel_info);
	pxafb_enable_controller(&panel_info);
}

/*----------------------------------------------------------------------*/
#if LCD_BPP == LCD_COLOR8
void
lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
{
	struct pxafb_info *fbi = &panel_info.pxa;
	unsigned short *palette = (unsigned short *)fbi->palette;
	u_int val;

	if (regno < fbi->palette_size) {
		val = ((red << 8) & 0xf800);
		val |= ((green << 4) & 0x07e0);
		val |= (blue & 0x001f);

#ifdef LCD_INVERT_COLORS
		palette[regno] = ~val;
#else
		palette[regno] = val;
#endif
	}

	debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %04X\n",
		regno, &palette[regno],
		red, green, blue,
		palette[regno]);
}
#endif /* LCD_COLOR8 */

/*----------------------------------------------------------------------*/
__weak void lcd_enable(void)
{
}

/************************************************************************/
/* ** PXA255 specific routines						*/
/************************************************************************/

/*
 * Calculate fb size for VIDEOLFB_ATAG. Size returned contains fb,
 * descriptors and palette areas.
 */
ulong calc_fbsize (void)
{
	ulong size;
	int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;

	size = line_length * panel_info.vl_row;
	size += PAGE_SIZE;

	return size;
}

static int pxafb_init_mem (void *lcdbase, vidinfo_t *vid)
{
	u_long palette_mem_size;
	struct pxafb_info *fbi = &vid->pxa;
	int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;

	fbi->screen = (u_long)lcdbase;

	fbi->palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16;
	palette_mem_size = fbi->palette_size * sizeof(u16);

	debug("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
	/* locate palette and descs at end of page following fb */
	fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;

	return 0;
}
#ifdef	CONFIG_CPU_MONAHANS
static inline void pxafb_setup_gpio (vidinfo_t *vid) {}
#else
static void pxafb_setup_gpio (vidinfo_t *vid)
{
	u_long lccr0;

	/*
	 * setup is based on type of panel supported
	 */

	lccr0 = vid->pxa.reg_lccr0;

	/* 4 bit interface */
	if ((lccr0 & LCCR0_CMS) && (lccr0 & LCCR0_SDS) && !(lccr0 & LCCR0_DPD))
	{
		debug("Setting GPIO for 4 bit data\n");
		/* bits 58-61 */
		writel(readl(GPDR1) | (0xf << 26), GPDR1);
		writel((readl(GAFR1_U) & ~(0xff << 20)) | (0xaa << 20),
			GAFR1_U);

		/* bits 74-77 */
		writel(readl(GPDR2) | (0xf << 10), GPDR2);
		writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
			GAFR2_L);
	}

	/* 8 bit interface */
	else if (((lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_DPD))) ||
		(!(lccr0 & LCCR0_CMS) && !(lccr0 & LCCR0_PAS) && !(lccr0 & LCCR0_SDS)))
	{
		debug("Setting GPIO for 8 bit data\n");
		/* bits 58-65 */
		writel(readl(GPDR1) | (0x3f << 26), GPDR1);
		writel(readl(GPDR2) | (0x3), GPDR2);

		writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
			GAFR1_U);
		writel((readl(GAFR2_L) & ~0xf) | (0xa), GAFR2_L);

		/* bits 74-77 */
		writel(readl(GPDR2) | (0xf << 10), GPDR2);
		writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20),
			GAFR2_L);
	}

	/* 16 bit interface */
	else if (!(lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) || (lccr0 & LCCR0_PAS)))
	{
		debug("Setting GPIO for 16 bit data\n");
		/* bits 58-77 */
		writel(readl(GPDR1) | (0x3f << 26), GPDR1);
		writel(readl(GPDR2) | 0x00003fff, GPDR2);

		writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20),
			GAFR1_U);
		writel((readl(GAFR2_L) & 0xf0000000) | 0x0aaaaaaa, GAFR2_L);
	}
	else
	{
		printf("pxafb_setup_gpio: unable to determine bits per pixel\n");
	}
}
#endif

static void pxafb_enable_controller (vidinfo_t *vid)
{
	debug("Enabling LCD controller\n");

	/* Sequence from 11.7.10 */
	writel(vid->pxa.reg_lccr3, LCCR3);
	writel(vid->pxa.reg_lccr2, LCCR2);
	writel(vid->pxa.reg_lccr1, LCCR1);
	writel(vid->pxa.reg_lccr0 & ~LCCR0_ENB, LCCR0);
	writel(vid->pxa.fdadr0, FDADR0);
	writel(vid->pxa.fdadr1, FDADR1);
	writel(readl(LCCR0) | LCCR0_ENB, LCCR0);

#ifdef	CONFIG_CPU_MONAHANS
	writel(readl(CKENA) | CKENA_1_LCD, CKENA);
#else
	writel(readl(CKEN) | CKEN16_LCD, CKEN);
#endif

	debug("FDADR0 = 0x%08x\n", readl(FDADR0));
	debug("FDADR1 = 0x%08x\n", readl(FDADR1));
	debug("LCCR0 = 0x%08x\n", readl(LCCR0));
	debug("LCCR1 = 0x%08x\n", readl(LCCR1));
	debug("LCCR2 = 0x%08x\n", readl(LCCR2));
	debug("LCCR3 = 0x%08x\n", readl(LCCR3));
}

static int pxafb_init (vidinfo_t *vid)
{
	struct pxafb_info *fbi = &vid->pxa;

	debug("Configuring PXA LCD\n");

	fbi->reg_lccr0 = REG_LCCR0;
	fbi->reg_lccr3 = REG_LCCR3;

	debug("vid: vl_col=%d hslen=%d lm=%d rm=%d\n",
		vid->vl_col, vid->vl_hpw,
		vid->vl_blw, vid->vl_elw);
	debug("vid: vl_row=%d vslen=%d um=%d bm=%d\n",
		vid->vl_row, vid->vl_vpw,
		vid->vl_bfw, vid->vl_efw);

	fbi->reg_lccr1 =
		LCCR1_DisWdth(vid->vl_col) +
		LCCR1_HorSnchWdth(vid->vl_hpw) +
		LCCR1_BegLnDel(vid->vl_blw) +
		LCCR1_EndLnDel(vid->vl_elw);

	fbi->reg_lccr2 =
		LCCR2_DisHght(vid->vl_row) +
		LCCR2_VrtSnchWdth(vid->vl_vpw) +
		LCCR2_BegFrmDel(vid->vl_bfw) +
		LCCR2_EndFrmDel(vid->vl_efw);

	fbi->reg_lccr3 = REG_LCCR3 & ~(LCCR3_HSP | LCCR3_VSP);
	fbi->reg_lccr3 |= (vid->vl_hsp ? LCCR3_HorSnchL : LCCR3_HorSnchH)
			| (vid->vl_vsp ? LCCR3_VrtSnchL : LCCR3_VrtSnchH);


	/* setup dma descriptors */
	fbi->dmadesc_fblow = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 3*16);
	fbi->dmadesc_fbhigh = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 2*16);
	fbi->dmadesc_palette = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette - 1*16);

	#define BYTES_PER_PANEL	((fbi->reg_lccr0 & LCCR0_SDS) ? \
		(vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8 / 2) : \
		(vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8))

	/* populate descriptors */
	fbi->dmadesc_fblow->fdadr = (u_long)fbi->dmadesc_fblow;
	fbi->dmadesc_fblow->fsadr = fbi->screen + BYTES_PER_PANEL;
	fbi->dmadesc_fblow->fidr  = 0;
	fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL;

	fbi->fdadr1 = (u_long)fbi->dmadesc_fblow; /* only used in dual-panel mode */

	fbi->dmadesc_fbhigh->fsadr = fbi->screen;
	fbi->dmadesc_fbhigh->fidr = 0;
	fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL;

	fbi->dmadesc_palette->fsadr = fbi->palette;
	fbi->dmadesc_palette->fidr  = 0;
	fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL;

	if( NBITS(vid->vl_bpix) < 12)
	{
		/* assume any mode with <12 bpp is palette driven */
		fbi->dmadesc_palette->fdadr = (u_long)fbi->dmadesc_fbhigh;
		fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_palette;
		/* flips back and forth between pal and fbhigh */
		fbi->fdadr0 = (u_long)fbi->dmadesc_palette;
	}
	else
	{
		/* palette shouldn't be loaded in true-color mode */
		fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_fbhigh;
		fbi->fdadr0 = (u_long)fbi->dmadesc_fbhigh; /* no pal just fbhigh */
	}

	debug("fbi->dmadesc_fblow = 0x%lx\n", (u_long)fbi->dmadesc_fblow);
	debug("fbi->dmadesc_fbhigh = 0x%lx\n", (u_long)fbi->dmadesc_fbhigh);
	debug("fbi->dmadesc_palette = 0x%lx\n", (u_long)fbi->dmadesc_palette);

	debug("fbi->dmadesc_fblow->fdadr = 0x%lx\n", fbi->dmadesc_fblow->fdadr);
	debug("fbi->dmadesc_fbhigh->fdadr = 0x%lx\n", fbi->dmadesc_fbhigh->fdadr);
	debug("fbi->dmadesc_palette->fdadr = 0x%lx\n", fbi->dmadesc_palette->fdadr);

	debug("fbi->dmadesc_fblow->fsadr = 0x%lx\n", fbi->dmadesc_fblow->fsadr);
	debug("fbi->dmadesc_fbhigh->fsadr = 0x%lx\n", fbi->dmadesc_fbhigh->fsadr);
	debug("fbi->dmadesc_palette->fsadr = 0x%lx\n", fbi->dmadesc_palette->fsadr);

	debug("fbi->dmadesc_fblow->ldcmd = 0x%lx\n", fbi->dmadesc_fblow->ldcmd);
	debug("fbi->dmadesc_fbhigh->ldcmd = 0x%lx\n", fbi->dmadesc_fbhigh->ldcmd);
	debug("fbi->dmadesc_palette->ldcmd = 0x%lx\n", fbi->dmadesc_palette->ldcmd);

	return 0;
}

/************************************************************************/
/************************************************************************/

#endif /* CONFIG_LCD */
Commit	Line	Data
71f95118	1	/*
8655b6f8 WD	2	* PXA LCD Controller
8655b6f8 WD	3	*
71f95118 WD	4	* (C) Copyright 2001-2002
	5	* Wolfgang Denk, DENX Software Engineering -- wd@denx.de
	6	*
3765b3e7	7	* SPDX-License-Identifier: GPL-2.0+
71f95118 WD	8	*/
	9
	10	/************************************************************************/
	11	/* ** HEADER FILES */
	12	/************************************************************************/
	13
71f95118	14	#include <common.h>
71f95118	15	#include <asm/arch/pxa-regs.h>
3ba8bf7c	16	#include <asm/io.h>
ab9272f9 MZ	17	#include <lcd.h>
	18	#include <linux/types.h>
	19	#include <stdarg.h>
	20	#include <stdio_dev.h>
71f95118	21
8655b6f8	22	/* #define DEBUG */
71f95118	23
8655b6f8	24	#ifdef CONFIG_LCD
71f95118 WD	25
71f95118 WD	26	/----------------------------------------------------------------------/
71f95118	27	/*
8655b6f8 WD	28	* Define panel bpp, LCCR0, LCCR3 and panel_info video struct for
8655b6f8 WD	29	* your display.
71f95118 WD	30	*/
71f95118 WD	31
8655b6f8 WD	32	#ifdef CONFIG_PXA_VGA
	33	/* LCD outputs connected to a video DAC */
	34	# define LCD_BPP LCD_COLOR8
71f95118 WD	35
71f95118 WD	36	/* you have to set lccr0 and lccr3 (including pcd) */
8655b6f8 WD	37	# define REG_LCCR0 0x003008f8
8655b6f8 WD	38	# define REG_LCCR3 0x0300FF01
71f95118 WD	39
71f95118 WD	40	/* 640x480x16 @ 61 Hz */
8655b6f8	41	vidinfo_t panel_info = {
9f80a20e MV	42	.vl_col = 640,
	43	.vl_row = 480,
	44	.vl_width = 640,
	45	.vl_height = 480,
	46	.vl_clkp = CONFIG_SYS_HIGH,
	47	.vl_oep = CONFIG_SYS_HIGH,
	48	.vl_hsp = CONFIG_SYS_HIGH,
	49	.vl_vsp = CONFIG_SYS_HIGH,
	50	.vl_dp = CONFIG_SYS_HIGH,
	51	.vl_bpix = LCD_BPP,
	52	.vl_lbw = 0,
	53	.vl_splt = 0,
	54	.vl_clor = 0,
	55	.vl_tft = 1,
	56	.vl_hpw = 40,
	57	.vl_blw = 56,
	58	.vl_elw = 56,
	59	.vl_vpw = 20,
	60	.vl_bfw = 8,
	61	.vl_efw = 8,
71f95118 WD	62	};
	63	#endif /* CONFIG_PXA_VIDEO */
	64
8655b6f8	65	/----------------------------------------------------------------------/
71f95118 WD	66	#ifdef CONFIG_SHARP_LM8V31
71f95118 WD	67
8655b6f8 WD	68	# define LCD_BPP LCD_COLOR8
8655b6f8 WD	69	# define LCD_INVERT_COLORS /* Needed for colors to be correct, but why? */
71f95118 WD	70
71f95118 WD	71	/* you have to set lccr0 and lccr3 (including pcd) */
8655b6f8 WD	72	# define REG_LCCR0 0x0030087C
	73	# define REG_LCCR3 0x0340FF08
	74
	75	vidinfo_t panel_info = {
9f80a20e MV	76	.vl_col = 640,
	77	.vl_row = 480,
	78	.vl_width = 157,
	79	.vl_height = 118,
	80	.vl_clkp = CONFIG_SYS_HIGH,
	81	.vl_oep = CONFIG_SYS_HIGH,
	82	.vl_hsp = CONFIG_SYS_HIGH,
	83	.vl_vsp = CONFIG_SYS_HIGH,
	84	.vl_dp = CONFIG_SYS_HIGH,
	85	.vl_bpix = LCD_BPP,
	86	.vl_lbw = 0,
	87	.vl_splt = 1,
	88	.vl_clor = 1,
	89	.vl_tft = 0,
	90	.vl_hpw = 1,
	91	.vl_blw = 3,
	92	.vl_elw = 3,
	93	.vl_vpw = 1,
	94	.vl_bfw = 0,
	95	.vl_efw = 0,
71f95118 WD	96	};
71f95118 WD	97	#endif /* CONFIG_SHARP_LM8V31 */
9b92cf04 MV	98	/----------------------------------------------------------------------/
	99	#ifdef CONFIG_VOIPAC_LCD
	100
	101	# define LCD_BPP LCD_COLOR8
	102	# define LCD_INVERT_COLORS
	103
	104	/* you have to set lccr0 and lccr3 (including pcd) */
	105	# define REG_LCCR0 0x043008f8
	106	# define REG_LCCR3 0x0340FF08
	107
	108	vidinfo_t panel_info = {
9f80a20e MV	109	.vl_col = 640,
	110	.vl_row = 480,
	111	.vl_width = 157,
	112	.vl_height = 118,
	113	.vl_clkp = CONFIG_SYS_HIGH,
	114	.vl_oep = CONFIG_SYS_HIGH,
	115	.vl_hsp = CONFIG_SYS_HIGH,
	116	.vl_vsp = CONFIG_SYS_HIGH,
	117	.vl_dp = CONFIG_SYS_HIGH,
	118	.vl_bpix = LCD_BPP,
	119	.vl_lbw = 0,
	120	.vl_splt = 1,
	121	.vl_clor = 1,
	122	.vl_tft = 1,
	123	.vl_hpw = 32,
	124	.vl_blw = 144,
	125	.vl_elw = 32,
	126	.vl_vpw = 2,
	127	.vl_bfw = 13,
	128	.vl_efw = 30,
9b92cf04 MV	129	};
9b92cf04 MV	130	#endif /* CONFIG_VOIPAC_LCD */
71f95118 WD	131
71f95118 WD	132	/----------------------------------------------------------------------/
8655b6f8 WD	133	#ifdef CONFIG_HITACHI_SX14
	134	/* Hitachi SX14Q004-ZZA color STN LCD */
	135	#define LCD_BPP LCD_COLOR8
71f95118	136
8655b6f8 WD	137	/* you have to set lccr0 and lccr3 (including pcd) */
	138	#define REG_LCCR0 0x00301079
	139	#define REG_LCCR3 0x0340FF20
	140
	141	vidinfo_t panel_info = {
9f80a20e MV	142	.vl_col = 320,
	143	.vl_row = 240,
	144	.vl_width = 167,
	145	.vl_height = 109,
	146	.vl_clkp = CONFIG_SYS_HIGH,
	147	.vl_oep = CONFIG_SYS_HIGH,
	148	.vl_hsp = CONFIG_SYS_HIGH,
	149	.vl_vsp = CONFIG_SYS_HIGH,
	150	.vl_dp = CONFIG_SYS_HIGH,
	151	.vl_bpix = LCD_BPP,
	152	.vl_lbw = 1,
	153	.vl_splt = 0,
	154	.vl_clor = 1,
	155	.vl_tft = 0,
	156	.vl_hpw = 1,
	157	.vl_blw = 1,
	158	.vl_elw = 1,
	159	.vl_vpw = 7,
	160	.vl_bfw = 0,
	161	.vl_efw = 0,
71f95118	162	};
8655b6f8	163	#endif /* CONFIG_HITACHI_SX14 */
71f95118	164
546cd608 MV	165	/----------------------------------------------------------------------/
	166	#ifdef CONFIG_LMS283GF05
	167
	168	# define LCD_BPP LCD_COLOR8
07517e7f	169	/# define LCD_INVERT_COLORS/
546cd608 MV	170
	171	/* you have to set lccr0 and lccr3 (including pcd) */
	172	# define REG_LCCR0 0x043008f8
	173	# define REG_LCCR3 0x03b00009
	174
	175	vidinfo_t panel_info = {
9f80a20e MV	176	.vl_col = 240,
	177	.vl_row = 320,
	178	.vl_width = 240,
	179	.vl_height = 320,
	180	.vl_clkp = CONFIG_SYS_HIGH,
	181	.vl_oep = CONFIG_SYS_LOW,
	182	.vl_hsp = CONFIG_SYS_LOW,
	183	.vl_vsp = CONFIG_SYS_LOW,
	184	.vl_dp = CONFIG_SYS_HIGH,
	185	.vl_bpix = LCD_BPP,
	186	.vl_lbw = 0,
	187	.vl_splt = 1,
	188	.vl_clor = 1,
	189	.vl_tft = 1,
	190	.vl_hpw = 4,
	191	.vl_blw = 4,
	192	.vl_elw = 8,
	193	.vl_vpw = 4,
	194	.vl_bfw = 4,
	195	.vl_efw = 8,
546cd608 MV	196	};
	197	#endif /* CONFIG_LMS283GF05 */
	198
71f95118 WD	199	/----------------------------------------------------------------------/
71f95118 WD	200
f7d58d91 MV	201	#ifdef CONFIG_ACX517AKN
	202
	203	# define LCD_BPP LCD_COLOR8
	204
	205	/* you have to set lccr0 and lccr3 (including pcd) */
	206	# define REG_LCCR0 0x003008f9
	207	# define REG_LCCR3 0x03700006
	208
	209	vidinfo_t panel_info = {
	210	.vl_col = 320,
	211	.vl_row = 320,
	212	.vl_width = 320,
	213	.vl_height = 320,
	214	.vl_clkp = CONFIG_SYS_HIGH,
	215	.vl_oep = CONFIG_SYS_LOW,
	216	.vl_hsp = CONFIG_SYS_LOW,
	217	.vl_vsp = CONFIG_SYS_LOW,
	218	.vl_dp = CONFIG_SYS_HIGH,
	219	.vl_bpix = LCD_BPP,
	220	.vl_lbw = 0,
	221	.vl_splt = 1,
	222	.vl_clor = 1,
	223	.vl_tft = 1,
	224	.vl_hpw = 0x04,
	225	.vl_blw = 0x1c,
	226	.vl_elw = 0x08,
	227	.vl_vpw = 0x01,
	228	.vl_bfw = 0x07,
	229	.vl_efw = 0x08,
	230	};
	231	#endif /* CONFIG_ACX517AKN */
	232
98eda338 MD	233	#ifdef CONFIG_ACX544AKN
	234
	235	# define LCD_BPP LCD_COLOR16
	236
	237	/* you have to set lccr0 and lccr3 (including pcd) */
	238	# define REG_LCCR0 0x003008f9
	239	# define REG_LCCR3 0x04700007 /* 16bpp */
	240
	241	vidinfo_t panel_info = {
	242	.vl_col = 320,
	243	.vl_row = 320,
	244	.vl_width = 320,
	245	.vl_height = 320,
	246	.vl_clkp = CONFIG_SYS_LOW,
	247	.vl_oep = CONFIG_SYS_LOW,
	248	.vl_hsp = CONFIG_SYS_LOW,
	249	.vl_vsp = CONFIG_SYS_LOW,
	250	.vl_dp = CONFIG_SYS_LOW,
	251	.vl_bpix = LCD_BPP,
	252	.vl_lbw = 0,
	253	.vl_splt = 0,
	254	.vl_clor = 1,
	255	.vl_tft = 1,
	256	.vl_hpw = 0x05,
	257	.vl_blw = 0x13,
	258	.vl_elw = 0x08,
	259	.vl_vpw = 0x02,
	260	.vl_bfw = 0x07,
	261	.vl_efw = 0x05,
	262	};
	263	#endif /* CONFIG_ACX544AKN */
	264
f7d58d91 MV	265	/----------------------------------------------------------------------/
f7d58d91 MV	266
42222be4 MV	267	#ifdef CONFIG_LQ038J7DH53
	268
	269	# define LCD_BPP LCD_COLOR8
	270
	271	/* you have to set lccr0 and lccr3 (including pcd) */
	272	# define REG_LCCR0 0x003008f9
	273	# define REG_LCCR3 0x03700004
	274
	275	vidinfo_t panel_info = {
	276	.vl_col = 320,
	277	.vl_row = 480,
	278	.vl_width = 320,
	279	.vl_height = 480,
	280	.vl_clkp = CONFIG_SYS_HIGH,
	281	.vl_oep = CONFIG_SYS_LOW,
	282	.vl_hsp = CONFIG_SYS_LOW,
	283	.vl_vsp = CONFIG_SYS_LOW,
	284	.vl_dp = CONFIG_SYS_HIGH,
	285	.vl_bpix = LCD_BPP,
	286	.vl_lbw = 0,
	287	.vl_splt = 1,
	288	.vl_clor = 1,
	289	.vl_tft = 1,
	290	.vl_hpw = 0x04,
	291	.vl_blw = 0x20,
	292	.vl_elw = 0x01,
	293	.vl_vpw = 0x01,
	294	.vl_bfw = 0x04,
	295	.vl_efw = 0x01,
	296	};
	297	#endif /* CONFIG_ACX517AKN */
	298
	299	/----------------------------------------------------------------------/
	300
8b71d2b7 MV	301	#ifdef CONFIG_LITTLETON_LCD
	302	# define LCD_BPP LCD_COLOR8
	303
	304	/* you have to set lccr0 and lccr3 (including pcd) */
	305	# define REG_LCCR0 0x003008f8
	306	# define REG_LCCR3 0x0300FF04
	307
	308	vidinfo_t panel_info = {
	309	.vl_col = 480,
	310	.vl_row = 640,
	311	.vl_width = 480,
	312	.vl_height = 640,
	313	.vl_clkp = CONFIG_SYS_HIGH,
	314	.vl_oep = CONFIG_SYS_HIGH,
	315	.vl_hsp = CONFIG_SYS_HIGH,
	316	.vl_vsp = CONFIG_SYS_HIGH,
	317	.vl_dp = CONFIG_SYS_HIGH,
	318	.vl_bpix = LCD_BPP,
	319	.vl_lbw = 0,
	320	.vl_splt = 0,
	321	.vl_clor = 0,
	322	.vl_tft = 1,
	323	.vl_hpw = 9,
	324	.vl_blw = 8,
	325	.vl_elw = 24,
	326	.vl_vpw = 2,
	327	.vl_bfw = 2,
	328	.vl_efw = 4,
	329	};
	330	#endif /* CONFIG_LITTLETON_LCD */
	331
	332	/----------------------------------------------------------------------/
	333
8655b6f8 WD	334	static int pxafb_init_mem (void lcdbase, vidinfo_t vid);
	335	static void pxafb_setup_gpio (vidinfo_t *vid);
	336	static void pxafb_enable_controller (vidinfo_t *vid);
	337	static int pxafb_init (vidinfo_t *vid);
71f95118	338
71f95118	339	/************************************************************************/
8655b6f8	340	/* --------------- PXA chipset specific functions ------------------- */
71f95118 WD	341	/************************************************************************/
71f95118 WD	342
38b55087 NK	343	ushort *configuration_get_cmap(void)
	344	{
	345	struct pxafb_info *fbi = &panel_info.pxa;
	346	return (ushort *)fbi->palette;
	347	}
	348
8655b6f8	349	void lcd_ctrl_init (void *lcdbase)
71f95118	350	{
8bde7f77	351	pxafb_init_mem(lcdbase, &panel_info);
71f95118 WD	352	pxafb_init(&panel_info);
	353	pxafb_setup_gpio(&panel_info);
	354	pxafb_enable_controller(&panel_info);
	355	}
	356
71f95118	357	/----------------------------------------------------------------------/
71f95118	358	#if LCD_BPP == LCD_COLOR8
8655b6f8	359	void
71f95118 WD	360	lcd_setcolreg (ushort regno, ushort red, ushort green, ushort blue)
	361	{
	362	struct pxafb_info *fbi = &panel_info.pxa;
	363	unsigned short palette = (unsigned short )fbi->palette;
	364	u_int val;
8bde7f77	365
71f95118 WD	366	if (regno < fbi->palette_size) {
	367	val = ((red << 8) & 0xf800);
	368	val \|= ((green << 4) & 0x07e0);
	369	val \|= (blue & 0x001f);
	370
	371	#ifdef LCD_INVERT_COLORS
	372	palette[regno] = ~val;
	373	#else
8655b6f8	374	palette[regno] = val;
71f95118 WD	375	#endif
	376	}
	377
	378	debug ("setcolreg: reg %2d @ %p: R=%02X G=%02X B=%02X => %04X\n",
	379	regno, &palette[regno],
	380	red, green, blue,
	381	palette[regno]);
	382	}
8655b6f8	383	#endif /* LCD_COLOR8 */
71f95118 WD	384
71f95118 WD	385	/----------------------------------------------------------------------/
86e929e8	386	__weak void lcd_enable(void)
71f95118	387	{
71f95118	388	}
71f95118	389
71f95118	390	/************************************************************************/
8655b6f8	391	/* ** PXA255 specific routines */
71f95118 WD	392	/************************************************************************/
71f95118 WD	393
8655b6f8 WD	394	/*
	395	* Calculate fb size for VIDEOLFB_ATAG. Size returned contains fb,
	396	* descriptors and palette areas.
	397	*/
	398	ulong calc_fbsize (void)
71f95118	399	{
8655b6f8 WD	400	ulong size;
8655b6f8 WD	401	int line_length = (panel_info.vl_col * NBITS (panel_info.vl_bpix)) / 8;
71f95118	402
8655b6f8 WD	403	size = line_length * panel_info.vl_row;
8655b6f8 WD	404	size += PAGE_SIZE;
71f95118	405
8655b6f8	406	return size;
71f95118 WD	407	}
71f95118 WD	408
8655b6f8	409	static int pxafb_init_mem (void lcdbase, vidinfo_t vid)
71f95118 WD	410	{
	411	u_long palette_mem_size;
	412	struct pxafb_info *fbi = &vid->pxa;
	413	int fb_size = vid->vl_row * (vid->vl_col * NBITS (vid->vl_bpix)) / 8;
	414
	415	fbi->screen = (u_long)lcdbase;
	416
	417	fbi->palette_size = NBITS(vid->vl_bpix) == 8 ? 256 : 16;
	418	palette_mem_size = fbi->palette_size * sizeof(u16);
8655b6f8	419
71f95118 WD	420	debug("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
71f95118 WD	421	/* locate palette and descs at end of page following fb */
8655b6f8	422	fbi->palette = (u_long)lcdbase + fb_size + PAGE_SIZE - palette_mem_size;
71f95118 WD	423
	424	return 0;
	425	}
8c35d0c5 MV	426	#ifdef CONFIG_CPU_MONAHANS
	427	static inline void pxafb_setup_gpio (vidinfo_t *vid) {}
	428	#else
8655b6f8	429	static void pxafb_setup_gpio (vidinfo_t *vid)
71f95118 WD	430	{
	431	u_long lccr0;
	432
	433	/*
	434	* setup is based on type of panel supported
	435	*/
	436
	437	lccr0 = vid->pxa.reg_lccr0;
	438
	439	/* 4 bit interface */
	440	if ((lccr0 & LCCR0_CMS) && (lccr0 & LCCR0_SDS) && !(lccr0 & LCCR0_DPD))
	441	{
	442	debug("Setting GPIO for 4 bit data\n");
	443	/* bits 58-61 */
3ba8bf7c MV	444	writel(readl(GPDR1) \| (0xf << 26), GPDR1);
	445	writel((readl(GAFR1_U) & ~(0xff << 20)) \| (0xaa << 20),
	446	GAFR1_U);
71f95118 WD	447
71f95118 WD	448	/* bits 74-77 */
3ba8bf7c MV	449	writel(readl(GPDR2) \| (0xf << 10), GPDR2);
	450	writel((readl(GAFR2_L) & ~(0xff << 20)) \| (0xaa << 20),
	451	GAFR2_L);
71f95118 WD	452	}
	453
	454	/* 8 bit interface */
	455	else if (((lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) \|\| (lccr0 & LCCR0_DPD))) \|\|
8655b6f8	456	(!(lccr0 & LCCR0_CMS) && !(lccr0 & LCCR0_PAS) && !(lccr0 & LCCR0_SDS)))
71f95118 WD	457	{
	458	debug("Setting GPIO for 8 bit data\n");
	459	/* bits 58-65 */
3ba8bf7c MV	460	writel(readl(GPDR1) \| (0x3f << 26), GPDR1);
3ba8bf7c MV	461	writel(readl(GPDR2) \| (0x3), GPDR2);
71f95118	462
3ba8bf7c MV	463	writel((readl(GAFR1_U) & ~(0xfff << 20)) \| (0xaaa << 20),
	464	GAFR1_U);
	465	writel((readl(GAFR2_L) & ~0xf) \| (0xa), GAFR2_L);
71f95118 WD	466
71f95118 WD	467	/* bits 74-77 */
3ba8bf7c MV	468	writel(readl(GPDR2) \| (0xf << 10), GPDR2);
	469	writel((readl(GAFR2_L) & ~(0xff << 20)) \| (0xaa << 20),
	470	GAFR2_L);
71f95118 WD	471	}
	472
	473	/* 16 bit interface */
	474	else if (!(lccr0 & LCCR0_CMS) && ((lccr0 & LCCR0_SDS) \|\| (lccr0 & LCCR0_PAS)))
	475	{
	476	debug("Setting GPIO for 16 bit data\n");
	477	/* bits 58-77 */
3ba8bf7c MV	478	writel(readl(GPDR1) \| (0x3f << 26), GPDR1);
3ba8bf7c MV	479	writel(readl(GPDR2) \| 0x00003fff, GPDR2);
71f95118	480
3ba8bf7c MV	481	writel((readl(GAFR1_U) & ~(0xfff << 20)) \| (0xaaa << 20),
	482	GAFR1_U);
	483	writel((readl(GAFR2_L) & 0xf0000000) \| 0x0aaaaaaa, GAFR2_L);
71f95118 WD	484	}
	485	else
	486	{
	487	printf("pxafb_setup_gpio: unable to determine bits per pixel\n");
	488	}
	489	}
8c35d0c5	490	#endif
71f95118	491
8655b6f8	492	static void pxafb_enable_controller (vidinfo_t *vid)
71f95118 WD	493	{
	494	debug("Enabling LCD controller\n");
	495
	496	/* Sequence from 11.7.10 */
3ba8bf7c MV	497	writel(vid->pxa.reg_lccr3, LCCR3);
	498	writel(vid->pxa.reg_lccr2, LCCR2);
	499	writel(vid->pxa.reg_lccr1, LCCR1);
	500	writel(vid->pxa.reg_lccr0 & ~LCCR0_ENB, LCCR0);
	501	writel(vid->pxa.fdadr0, FDADR0);
	502	writel(vid->pxa.fdadr1, FDADR1);
	503	writel(readl(LCCR0) \| LCCR0_ENB, LCCR0);
71f95118	504
8c35d0c5	505	#ifdef CONFIG_CPU_MONAHANS
3ba8bf7c	506	writel(readl(CKENA) \| CKENA_1_LCD, CKENA);
8c35d0c5	507	#else
3ba8bf7c	508	writel(readl(CKEN) \| CKEN16_LCD, CKEN);
8c35d0c5	509	#endif
71f95118	510
3ba8bf7c MV	511	debug("FDADR0 = 0x%08x\n", readl(FDADR0));
	512	debug("FDADR1 = 0x%08x\n", readl(FDADR1));
	513	debug("LCCR0 = 0x%08x\n", readl(LCCR0));
	514	debug("LCCR1 = 0x%08x\n", readl(LCCR1));
	515	debug("LCCR2 = 0x%08x\n", readl(LCCR2));
	516	debug("LCCR3 = 0x%08x\n", readl(LCCR3));
71f95118 WD	517	}
71f95118 WD	518
8655b6f8	519	static int pxafb_init (vidinfo_t *vid)
71f95118 WD	520	{
	521	struct pxafb_info *fbi = &vid->pxa;
	522
	523	debug("Configuring PXA LCD\n");
	524
	525	fbi->reg_lccr0 = REG_LCCR0;
	526	fbi->reg_lccr3 = REG_LCCR3;
	527
	528	debug("vid: vl_col=%d hslen=%d lm=%d rm=%d\n",
	529	vid->vl_col, vid->vl_hpw,
	530	vid->vl_blw, vid->vl_elw);
	531	debug("vid: vl_row=%d vslen=%d um=%d bm=%d\n",
	532	vid->vl_row, vid->vl_vpw,
	533	vid->vl_bfw, vid->vl_efw);
	534
	535	fbi->reg_lccr1 =
	536	LCCR1_DisWdth(vid->vl_col) +
	537	LCCR1_HorSnchWdth(vid->vl_hpw) +
	538	LCCR1_BegLnDel(vid->vl_blw) +
	539	LCCR1_EndLnDel(vid->vl_elw);
8bde7f77	540
71f95118 WD	541	fbi->reg_lccr2 =
	542	LCCR2_DisHght(vid->vl_row) +
	543	LCCR2_VrtSnchWdth(vid->vl_vpw) +
	544	LCCR2_BegFrmDel(vid->vl_bfw) +
	545	LCCR2_EndFrmDel(vid->vl_efw);
	546
8bde7f77	547	fbi->reg_lccr3 = REG_LCCR3 & ~(LCCR3_HSP \| LCCR3_VSP);
8655b6f8 WD	548	fbi->reg_lccr3 \|= (vid->vl_hsp ? LCCR3_HorSnchL : LCCR3_HorSnchH)
8655b6f8 WD	549	\| (vid->vl_vsp ? LCCR3_VrtSnchL : LCCR3_VrtSnchH);
8bde7f77	550
71f95118 WD	551
	552	/* setup dma descriptors */
	553	fbi->dmadesc_fblow = (struct pxafb_dma_descriptor )((unsigned int)fbi->palette - 316);
	554	fbi->dmadesc_fbhigh = (struct pxafb_dma_descriptor )((unsigned int)fbi->palette - 216);
	555	fbi->dmadesc_palette = (struct pxafb_dma_descriptor )((unsigned int)fbi->palette - 116);
	556
	557	#define BYTES_PER_PANEL ((fbi->reg_lccr0 & LCCR0_SDS) ? \
8bde7f77 WD	558	(vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8 / 2) : \
	559	(vid->vl_col * vid->vl_row * NBITS(vid->vl_bpix) / 8))
	560
71f95118 WD	561	/* populate descriptors */
	562	fbi->dmadesc_fblow->fdadr = (u_long)fbi->dmadesc_fblow;
	563	fbi->dmadesc_fblow->fsadr = fbi->screen + BYTES_PER_PANEL;
	564	fbi->dmadesc_fblow->fidr = 0;
	565	fbi->dmadesc_fblow->ldcmd = BYTES_PER_PANEL;
	566
	567	fbi->fdadr1 = (u_long)fbi->dmadesc_fblow; /* only used in dual-panel mode */
8bde7f77	568
71f95118 WD	569	fbi->dmadesc_fbhigh->fsadr = fbi->screen;
	570	fbi->dmadesc_fbhigh->fidr = 0;
	571	fbi->dmadesc_fbhigh->ldcmd = BYTES_PER_PANEL;
	572
	573	fbi->dmadesc_palette->fsadr = fbi->palette;
	574	fbi->dmadesc_palette->fidr = 0;
	575	fbi->dmadesc_palette->ldcmd = (fbi->palette_size * 2) \| LDCMD_PAL;
	576
	577	if( NBITS(vid->vl_bpix) < 12)
	578	{
	579	/* assume any mode with <12 bpp is palette driven */
	580	fbi->dmadesc_palette->fdadr = (u_long)fbi->dmadesc_fbhigh;
	581	fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_palette;
	582	/* flips back and forth between pal and fbhigh */
8bde7f77	583	fbi->fdadr0 = (u_long)fbi->dmadesc_palette;
71f95118 WD	584	}
	585	else
	586	{
	587	/* palette shouldn't be loaded in true-color mode */
	588	fbi->dmadesc_fbhigh->fdadr = (u_long)fbi->dmadesc_fbhigh;
	589	fbi->fdadr0 = (u_long)fbi->dmadesc_fbhigh; /* no pal just fbhigh */
	590	}
	591
	592	debug("fbi->dmadesc_fblow = 0x%lx\n", (u_long)fbi->dmadesc_fblow);
	593	debug("fbi->dmadesc_fbhigh = 0x%lx\n", (u_long)fbi->dmadesc_fbhigh);
	594	debug("fbi->dmadesc_palette = 0x%lx\n", (u_long)fbi->dmadesc_palette);
	595
	596	debug("fbi->dmadesc_fblow->fdadr = 0x%lx\n", fbi->dmadesc_fblow->fdadr);
	597	debug("fbi->dmadesc_fbhigh->fdadr = 0x%lx\n", fbi->dmadesc_fbhigh->fdadr);
	598	debug("fbi->dmadesc_palette->fdadr = 0x%lx\n", fbi->dmadesc_palette->fdadr);
	599
	600	debug("fbi->dmadesc_fblow->fsadr = 0x%lx\n", fbi->dmadesc_fblow->fsadr);
	601	debug("fbi->dmadesc_fbhigh->fsadr = 0x%lx\n", fbi->dmadesc_fbhigh->fsadr);
	602	debug("fbi->dmadesc_palette->fsadr = 0x%lx\n", fbi->dmadesc_palette->fsadr);
	603
	604	debug("fbi->dmadesc_fblow->ldcmd = 0x%lx\n", fbi->dmadesc_fblow->ldcmd);
	605	debug("fbi->dmadesc_fbhigh->ldcmd = 0x%lx\n", fbi->dmadesc_fbhigh->ldcmd);
	606	debug("fbi->dmadesc_palette->ldcmd = 0x%lx\n", fbi->dmadesc_palette->ldcmd);
8bde7f77	607
71f95118 WD	608	return 0;
	609	}
	610
	611	/************************************************************************/
	612	/************************************************************************/
	613
	614	#endif /* CONFIG_LCD */