[J-u-boot.git] / include / configs / ORSG.h

/*
 * (C) Copyright 2001
 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
#define CONFIG_ORSG		1	/* ...on a ORSG board		*/

#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/

#define CONFIG_SYS_CLK_FREQ	33000000 /* external frequency to pll	*/

#define CONFIG_BAUDRATE		9600
#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND "go fff00100"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		0	/* PHY address			*/
#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_PCI
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_ELF
#define CONFIG_CMD_BSP
#define CONFIG_CMD_EEPROM


#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/

#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
#define CFG_IGNORE_405_UART_ERRATA_59	/* ignore ppc405gp errata #59	*/
#define CFG_BASE_BAUD	    691200

/* The following table includes the supported baudrates */
#define CFG_BAUDRATE_TABLE	\
	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
	 57600, 115200, 230400, 460800, 921600 }

#define CFG_LOAD_ADDR	0x100000	/* default load address */
#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */

#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */

#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
#define PCI_HOST_FORCE	1		/* configure as pci host	*/
#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/

#define CONFIG_PCI			/* include pci support		*/
#define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci adapter		*/
#undef	CONFIG_PCI_PNP			/* no pci plug-and-play		*/
					/* resource configuration	*/

#undef	CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/

#define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
#define CFG_PCI_SUBSYS_DEVICEID 0x0411	/* PCI Device ID: ORSG		*/
#define CFG_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
#define CFG_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
#define CFG_PCI_PTM2LA	0xffc00000	/* point to flash		*/
#define CFG_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
#define CFG_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0xFFFD0000
#define CFG_MONITOR_BASE	CFG_FLASH_BASE
#define CFG_MONITOR_LEN		(192 * 1024)	/* Reserve 192 kB for Monitor	*/
#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CFG_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
#define CFG_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
#define CFG_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
/*
 * The following defines are added for buggy IOP480 byte interface.
 * All other boards should use the standard values (CPCI405 etc.)
 */
#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/

#define CFG_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */

#if 0 /* Use NVRAM for environment variables */
/*-----------------------------------------------------------------------
 * NVRAM organization
 */
#define CONFIG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
#define CFG_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
#define CFG_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
#define CONFIG_ENV_SIZE		0x1000		/* Size of Environment vars	*/
#define CONFIG_ENV_ADDR		\
	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CONFIG_ENV_SIZE)	/* Env	*/
#define CFG_NVRAM_VXWORKS_OFFS	0x6900		/* Offset for VxWorks eth-addr	*/

#else /* Use EEPROM for environment variables */

#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
#define CONFIG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
#define CONFIG_ENV_SIZE		0x300	/* 768 bytes may be used for env vars */
				   /* total size of a CAT24WC08 is 1024 bytes */
#endif

/*-----------------------------------------------------------------------
 * I2C EEPROM (CAT24WC08) for environment
 */
#define CONFIG_HARD_I2C			/* I2c with hardware support */
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
#define CFG_I2C_SLAVE		0x7F

#define CFG_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
#define CFG_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
/* mask of address bits that overflow into the "EEPROM chip address"	*/
#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
#define CFG_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
					/* 16 byte page write mode using*/
					/* last 4 bits of the address	*/
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0xFFC00000	/* FLASH bank #1	*/

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 */

/* Memory Bank 0 (Flash Bank 0) initialization					*/
#define CFG_EBC_PB0AP		0x92015480
#define CFG_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */

/* Memory Bank 1 (Flash Bank 1) initialization					*/
#define CFG_EBC_PB1AP		0x92015480
#define CFG_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */

/* Memory Bank 2 (PLD - FPGA-boot) initialization				*/
#define CFG_EBC_PB2AP		0x02015480  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
#define CFG_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 3 (PLD - OSL) initialization					*/
#define CFG_EBC_PB3AP		0x02015480  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
#define CFG_EBC_PB3CR		0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit	*/

/* Memory Bank 4 (Spartan2 1) initialization					*/
#define CFG_EBC_PB4AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
#define CFG_EBC_PB4CR		0xF209C000  /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/

/* Memory Bank 5 (Spartan2 2) initialization					*/
#define CFG_EBC_PB5AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
#define CFG_EBC_PB5CR		0xF309C000  /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/

/* Memory Bank 6 (Virtex 1) initialization					*/
#define CFG_EBC_PB6AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
#define CFG_EBC_PB6CR		0xF409A000  /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/

/* Memory Bank 7 (Virtex 2) initialization					*/
#define CFG_EBC_PB7AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
#define CFG_EBC_PB7CR		0xF509A000  /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/


#define CFG_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */

/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
#define CFG_TEMP_STACK_OCM	  1

/* On Chip Memory location */
#define CFG_OCM_DATA_ADDR	0xF8000000
#define CFG_OCM_DATA_SIZE	0x1000

#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR /* inside of SDRAM		*/
#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE /* End of used area in RAM	*/
#define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET


/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#endif	/* __CONFIG_H */
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2001
	3	* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/*
	32	* High Level Configuration Options
	33	* (easy to change)
	34	*/
	35
	36	#define CONFIG_405GP 1 /* This is a PPC405 CPU */
c837dcb1 WD	37	#define CONFIG_4xx 1 /* ...member of PPC4xx family */
c837dcb1 WD	38	#define CONFIG_ORSG 1 /* ...on a ORSG board */
c609719b	39
c837dcb1	40	#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
c609719b	41
c837dcb1	42	#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
c609719b WD	43
	44	#define CONFIG_BAUDRATE 9600
	45	#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
	46
	47	#undef CONFIG_BOOTARGS
	48	#define CONFIG_BOOTCOMMAND "go fff00100"
	49
	50	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	51	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	52
	53	#define CONFIG_MII 1 /* MII PHY management */
c837dcb1	54	#define CONFIG_PHY_ADDR 0 /* PHY address */
a20b27a3	55	#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
c609719b	56
e18a1061	57
659e2f67 JL	58	/*
	59	* BOOTP options
	60	*/
	61	#define CONFIG_BOOTP_BOOTFILESIZE
	62	#define CONFIG_BOOTP_BOOTPATH
	63	#define CONFIG_BOOTP_GATEWAY
	64	#define CONFIG_BOOTP_HOSTNAME
	65
	66
e18a1061 JL	67	/*
	68	* Command line configuration.
	69	*/
	70	#include <config_cmd_default.h>
	71
	72	#define CONFIG_CMD_PCI
	73	#define CONFIG_CMD_IRQ
	74	#define CONFIG_CMD_ASKENV
	75	#define CONFIG_CMD_ELF
	76	#define CONFIG_CMD_BSP
	77	#define CONFIG_CMD_EEPROM
	78
c609719b WD	79
	80	#define CONFIG_MAC_PARTITION
	81	#define CONFIG_DOS_PARTITION
	82
c837dcb1	83	#undef CONFIG_WATCHDOG /* watchdog disabled */
c609719b	84
c837dcb1	85	#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
c609719b WD	86
	87	/*
	88	* Miscellaneous configurable options
	89	*/
	90	#define CFG_LONGHELP /* undef to save memory */
	91	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
e18a1061	92	#if defined(CONFIG_CMD_KGDB)
c837dcb1	93	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
c609719b	94	#else
c837dcb1	95	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
c609719b WD	96	#endif
	97	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	98	#define CFG_MAXARGS 16 /* max number of command args */
	99	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	100
c837dcb1	101	#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
c609719b WD	102
	103	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
	104	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
	105
c837dcb1 WD	106	#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
	107	#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
	108	#define CFG_BASE_BAUD 691200
c609719b WD	109
c609719b WD	110	/* The following table includes the supported baudrates */
c837dcb1	111	#define CFG_BAUDRATE_TABLE \
8bde7f77 WD	112	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
8bde7f77 WD	113	57600, 115200, 230400, 460800, 921600 }
c609719b WD	114
	115	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	116	#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
	117
c837dcb1	118	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
c609719b WD	119
	120	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
	121
	122	/*-----------------------------------------------------------------------
	123	* PCI stuff
	124	*-----------------------------------------------------------------------
	125	*/
c837dcb1 WD	126	#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
	127	#define PCI_HOST_FORCE 1 /* configure as pci host */
	128	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
	129
	130	#define CONFIG_PCI /* include pci support */
	131	#define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci adapter */
	132	#undef CONFIG_PCI_PNP /* no pci plug-and-play */
	133	/* resource configuration */
	134
	135	#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
	136
	137	#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
	138	#define CFG_PCI_SUBSYS_DEVICEID 0x0411 /* PCI Device ID: ORSG */
	139	#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
	140	#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
	141	#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
	142	#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
	143	#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
	144	#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
	145	#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
c609719b WD	146
	147	/*-----------------------------------------------------------------------
	148	* Start addresses for the final memory configuration
	149	* (Set up by the startup code)
	150	* Please note that CFG_SDRAM_BASE _must_ start at 0
	151	*/
	152	#define CFG_SDRAM_BASE 0x00000000
	153	#define CFG_FLASH_BASE 0xFFFD0000
	154	#define CFG_MONITOR_BASE CFG_FLASH_BASE
	155	#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */
	156	#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
	157
	158	/*
	159	* For booting Linux, the board info and command line data
	160	* have to be in the first 8 MB of memory, since this is
	161	* the maximum mapped by the Linux kernel during initialization.
	162	*/
	163	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	164	/*-----------------------------------------------------------------------
	165	* FLASH organization
	166	*/
	167	#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
	168	#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
	169
	170	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	171	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	172
c837dcb1 WD	173	#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
	174	#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
	175	#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
c609719b WD	176	/*
	177	* The following defines are added for buggy IOP480 byte interface.
	178	* All other boards should use the standard values (CPCI405 etc.)
	179	*/
c837dcb1 WD	180	#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
	181	#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
	182	#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
c609719b	183
c837dcb1	184	#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
c609719b WD	185
	186	#if 0 /* Use NVRAM for environment variables */
	187	/*-----------------------------------------------------------------------
	188	* NVRAM organization
	189	*/
9314cee6	190	#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
c609719b WD	191	#define CFG_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
c609719b WD	192	#define CFG_NVRAM_SIZE (321024) / NVRAM size */
0e8d1586 JCPV	193	#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
	194	#define CONFIG_ENV_ADDR \
	195	(CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */
c609719b WD	196	#define CFG_NVRAM_VXWORKS_OFFS 0x6900 /* Offset for VxWorks eth-addr */
	197
	198	#else /* Use EEPROM for environment variables */
	199
bb1f8b4f	200	#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
0e8d1586 JCPV	201	#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
0e8d1586 JCPV	202	#define CONFIG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */
8bde7f77	203	/* total size of a CAT24WC08 is 1024 bytes */
c609719b WD	204	#endif
	205
	206	/*-----------------------------------------------------------------------
	207	* I2C EEPROM (CAT24WC08) for environment
	208	*/
	209	#define CONFIG_HARD_I2C /* I2c with hardware support */
	210	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
	211	#define CFG_I2C_SLAVE 0x7F
	212
	213	#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
c837dcb1 WD	214	#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
c837dcb1 WD	215	/* mask of address bits that overflow into the "EEPROM chip address" */
c609719b WD	216	#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
	217	#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
	218	/* 16 byte page write mode using*/
c837dcb1	219	/* last 4 bits of the address */
c609719b WD	220	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
	221	#define CFG_EEPROM_PAGE_WRITE_ENABLE
	222
c609719b WD	223	/*
	224	* Init Memory Controller:
	225	*
	226	* BR0/1 and OR0/1 (FLASH)
	227	*/
	228
	229	#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
	230	#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
	231
	232	/*-----------------------------------------------------------------------
	233	* External Bus Controller (EBC) Setup
	234	*/
	235
c837dcb1 WD	236	/* Memory Bank 0 (Flash Bank 0) initialization */
	237	#define CFG_EBC_PB0AP 0x92015480
	238	#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
c609719b	239
c837dcb1 WD	240	/* Memory Bank 1 (Flash Bank 1) initialization */
	241	#define CFG_EBC_PB1AP 0x92015480
	242	#define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
c609719b	243
c837dcb1 WD	244	/* Memory Bank 2 (PLD - FPGA-boot) initialization */
c837dcb1 WD	245	#define CFG_EBC_PB2AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
8bde7f77	246	/* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
c837dcb1	247	#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
c609719b	248
c837dcb1 WD	249	/* Memory Bank 3 (PLD - OSL) initialization */
c837dcb1 WD	250	#define CFG_EBC_PB3AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
8bde7f77	251	/* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
c837dcb1	252	#define CFG_EBC_PB3CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
c609719b	253
c837dcb1 WD	254	/* Memory Bank 4 (Spartan2 1) initialization */
c837dcb1 WD	255	#define CFG_EBC_PB4AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
8bde7f77	256	/* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
c837dcb1	257	#define CFG_EBC_PB4CR 0xF209C000 /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/
c609719b	258
c837dcb1 WD	259	/* Memory Bank 5 (Spartan2 2) initialization */
c837dcb1 WD	260	#define CFG_EBC_PB5AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
8bde7f77	261	/* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
c837dcb1	262	#define CFG_EBC_PB5CR 0xF309C000 /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/
c609719b	263
c837dcb1 WD	264	/* Memory Bank 6 (Virtex 1) initialization */
c837dcb1 WD	265	#define CFG_EBC_PB6AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
8bde7f77	266	/* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
c837dcb1	267	#define CFG_EBC_PB6CR 0xF409A000 /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/
c609719b	268
c837dcb1 WD	269	/* Memory Bank 7 (Virtex 2) initialization */
c837dcb1 WD	270	#define CFG_EBC_PB7AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
8bde7f77	271	/* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
c837dcb1	272	#define CFG_EBC_PB7CR 0xF509A000 /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/
c609719b WD	273
c609719b WD	274
a20b27a3	275	#define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
c609719b WD	276
	277	/*-----------------------------------------------------------------------
	278	* Definitions for initial stack pointer and data area (in DPRAM)
	279	*/
	280
	281	/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
c837dcb1	282	#define CFG_TEMP_STACK_OCM 1
c609719b WD	283
	284	/* On Chip Memory location */
	285	#define CFG_OCM_DATA_ADDR 0xF8000000
	286	#define CFG_OCM_DATA_SIZE 0x1000
	287
	288	#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
	289	#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
	290	#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
	291	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
c837dcb1	292	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
c609719b WD	293
	294
	295	/*
	296	* Internal Definitions
	297	*
	298	* Boot Flags
	299	*/
	300	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	301	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	302
	303	#endif /* __CONFIG_H */