[J-u-boot.git] / drivers / mmc / davinci_mmc.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Davinci MMC Controller Driver
 *
 * Copyright (C) 2010 Texas Instruments Incorporated
 */

#include <config.h>
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <mmc.h>
#include <command.h>
#include <part.h>
#include <malloc.h>
#include <asm/io.h>
#include <asm/arch/sdmmc_defs.h>
#include <asm-generic/gpio.h>

#define DAVINCI_MAX_BLOCKS	(32)
#define WATCHDOG_COUNT		(100000)

#define get_val(addr)		REG(addr)
#define set_val(addr, val)	REG(addr) = (val)
#define set_bit(addr, val)	set_val((addr), (get_val(addr) | (val)))
#define clear_bit(addr, val)	set_val((addr), (get_val(addr) & ~(val)))

#ifdef CONFIG_DM_MMC
/* Davinci MMC board definitions */
struct davinci_mmc_priv {
	struct davinci_mmc_regs *reg_base;	/* Register base address */
	uint input_clk;		/* Input clock to MMC controller */
	struct gpio_desc cd_gpio;       /* Card Detect GPIO */
	struct gpio_desc wp_gpio;       /* Write Protect GPIO */
};

struct davinci_mmc_plat
{
	struct mmc_config cfg;
	struct mmc mmc;
};
#endif

/* Set davinci clock prescalar value based on the required clock in HZ */
#if !CONFIG_IS_ENABLED(DM_MMC)
static void dmmc_set_clock(struct mmc *mmc, uint clock)
{
	struct davinci_mmc *host = mmc->priv;
#else

static void davinci_mmc_set_clock(struct udevice *dev, uint clock)
{
	struct davinci_mmc_priv *host = dev_get_priv(dev);
        struct mmc *mmc = mmc_get_mmc_dev(dev);
#endif
	struct davinci_mmc_regs *regs = host->reg_base;
	uint clkrt, sysclk2, act_clock;

	if (clock < mmc->cfg->f_min)
		clock = mmc->cfg->f_min;
	if (clock > mmc->cfg->f_max)
		clock = mmc->cfg->f_max;

	set_val(&regs->mmcclk, 0);
	sysclk2 = host->input_clk;
	clkrt = (sysclk2 / (2 * clock)) - 1;

	/* Calculate the actual clock for the divider used */
	act_clock = (sysclk2 / (2 * (clkrt + 1)));

	/* Adjust divider if actual clock exceeds the required clock */
	if (act_clock > clock)
		clkrt++;

	/* check clock divider boundary and correct it */
	if (clkrt > 0xFF)
		clkrt = 0xFF;

	set_val(&regs->mmcclk, (clkrt | MMCCLK_CLKEN));
}

/* Status bit wait loop for MMCST1 */
static int
dmmc_wait_fifo_status(volatile struct davinci_mmc_regs *regs, uint status)
{
	uint wdog = WATCHDOG_COUNT;

	while (--wdog && ((get_val(&regs->mmcst1) & status) != status))
		udelay(10);

	if (!(get_val(&regs->mmcctl) & MMCCTL_WIDTH_4_BIT))
		udelay(100);

	if (wdog == 0)
		return -ECOMM;

	return 0;
}

/* Busy bit wait loop for MMCST1 */
static int dmmc_busy_wait(volatile struct davinci_mmc_regs *regs)
{
	uint wdog = WATCHDOG_COUNT;

	while (--wdog && (get_val(&regs->mmcst1) & MMCST1_BUSY))
		udelay(10);

	if (wdog == 0)
		return -ECOMM;

	return 0;
}

/* Status bit wait loop for MMCST0 - Checks for error bits as well */
static int dmmc_check_status(volatile struct davinci_mmc_regs *regs,
		uint *cur_st, uint st_ready, uint st_error)
{
	uint wdog = WATCHDOG_COUNT;
	uint mmcstatus = *cur_st;

	while (wdog--) {
		if (mmcstatus & st_ready) {
			*cur_st = mmcstatus;
			mmcstatus = get_val(&regs->mmcst1);
			return 0;
		} else if (mmcstatus & st_error) {
			if (mmcstatus & MMCST0_TOUTRS)
				return -ETIMEDOUT;
			printf("[ ST0 ERROR %x]\n", mmcstatus);
			/*
			 * Ignore CRC errors as some MMC cards fail to
			 * initialize on DM365-EVM on the SD1 slot
			 */
			if (mmcstatus & MMCST0_CRCRS)
				return 0;
			return -ECOMM;
		}
		udelay(10);

		mmcstatus = get_val(&regs->mmcst0);
	}

	printf("Status %x Timeout ST0:%x ST1:%x\n", st_ready, mmcstatus,
			get_val(&regs->mmcst1));
	return -ECOMM;
}

/*
 * Sends a command out on the bus.  Takes the device pointer,
 * a command pointer, and an optional data pointer.
 */
#if !CONFIG_IS_ENABLED(DM_MMC)
static int dmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
{
	struct davinci_mmc *host = mmc->priv;
#else
static int
davinci_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, struct mmc_data *data)
{
	struct davinci_mmc_priv *host = dev_get_priv(dev);
#endif
	volatile struct davinci_mmc_regs *regs = host->reg_base;
	uint mmcstatus, status_rdy, status_err;
	uint i, cmddata, bytes_left = 0;
	int fifo_words, fifo_bytes, err;
	char *data_buf = NULL;

	/* Clear status registers */
	mmcstatus = get_val(&regs->mmcst0);
	fifo_words = 16;
	fifo_bytes = fifo_words << 2;

	/* Wait for any previous busy signal to be cleared */
	dmmc_busy_wait(regs);

	cmddata = cmd->cmdidx;
	cmddata |= MMCCMD_PPLEN;

	/* Send init clock for CMD0 */
	if (cmd->cmdidx == MMC_CMD_GO_IDLE_STATE)
		cmddata |= MMCCMD_INITCK;

	switch (cmd->resp_type) {
	case MMC_RSP_R1b:
		cmddata |= MMCCMD_BSYEXP;
		/* Fall-through */
	case MMC_RSP_R1:    /* R1, R1b, R5, R6, R7 */
		cmddata |= MMCCMD_RSPFMT_R1567;
		break;
	case MMC_RSP_R2:
		cmddata |= MMCCMD_RSPFMT_R2;
		break;
	case MMC_RSP_R3: /* R3, R4 */
		cmddata |= MMCCMD_RSPFMT_R3;
		break;
	}

	set_val(&regs->mmcim, 0);

	if (data) {
		/* clear previous data transfer if any and set new one */
		bytes_left = (data->blocksize * data->blocks);

		/* Reset FIFO - Always use 32 byte fifo threshold */
		set_val(&regs->mmcfifoctl,
				(MMCFIFOCTL_FIFOLEV | MMCFIFOCTL_FIFORST));

		cmddata |= MMCCMD_DMATRIG;

		cmddata |= MMCCMD_WDATX;
		if (data->flags == MMC_DATA_READ) {
			set_val(&regs->mmcfifoctl, MMCFIFOCTL_FIFOLEV);
		} else if (data->flags == MMC_DATA_WRITE) {
			set_val(&regs->mmcfifoctl,
					(MMCFIFOCTL_FIFOLEV |
					 MMCFIFOCTL_FIFODIR));
			cmddata |= MMCCMD_DTRW;
		}

		set_val(&regs->mmctod, 0xFFFF);
		set_val(&regs->mmcnblk, (data->blocks & MMCNBLK_NBLK_MASK));
		set_val(&regs->mmcblen, (data->blocksize & MMCBLEN_BLEN_MASK));

		if (data->flags == MMC_DATA_WRITE) {
			uint val;
			data_buf = (char *)data->src;
			/* For write, fill FIFO with data before issue of CMD */
			for (i = 0; (i < fifo_words) && bytes_left; i++) {
				memcpy((char *)&val, data_buf, 4);
				set_val(&regs->mmcdxr, val);
				data_buf += 4;
				bytes_left -= 4;
			}
		}
	} else {
		set_val(&regs->mmcblen, 0);
		set_val(&regs->mmcnblk, 0);
	}

	set_val(&regs->mmctor, 0x1FFF);

	/* Send the command */
	set_val(&regs->mmcarghl, cmd->cmdarg);
	set_val(&regs->mmccmd, cmddata);

	status_rdy = MMCST0_RSPDNE;
	status_err = (MMCST0_TOUTRS | MMCST0_TOUTRD |
			MMCST0_CRCWR | MMCST0_CRCRD);
	if (cmd->resp_type & MMC_RSP_CRC)
		status_err |= MMCST0_CRCRS;

	mmcstatus = get_val(&regs->mmcst0);
	err = dmmc_check_status(regs, &mmcstatus, status_rdy, status_err);
	if (err)
		return err;

	/* For R1b wait for busy done */
	if (cmd->resp_type == MMC_RSP_R1b)
		dmmc_busy_wait(regs);

	/* Collect response from controller for specific commands */
	if (mmcstatus & MMCST0_RSPDNE) {
		/* Copy the response to the response buffer */
		if (cmd->resp_type & MMC_RSP_136) {
			cmd->response[0] = get_val(&regs->mmcrsp67);
			cmd->response[1] = get_val(&regs->mmcrsp45);
			cmd->response[2] = get_val(&regs->mmcrsp23);
			cmd->response[3] = get_val(&regs->mmcrsp01);
		} else if (cmd->resp_type & MMC_RSP_PRESENT) {
			cmd->response[0] = get_val(&regs->mmcrsp67);
		}
	}

	if (data == NULL)
		return 0;

	if (data->flags == MMC_DATA_READ) {
		/* check for DATDNE along with DRRDY as the controller might
		 * set the DATDNE without DRRDY for smaller transfers with
		 * less than FIFO threshold bytes
		 */
		status_rdy = MMCST0_DRRDY | MMCST0_DATDNE;
		status_err = MMCST0_TOUTRD | MMCST0_CRCRD;
		data_buf = data->dest;
	} else {
		status_rdy = MMCST0_DXRDY | MMCST0_DATDNE;
		status_err = MMCST0_CRCWR;
	}

	/* Wait until all of the blocks are transferred */
	while (bytes_left) {
		err = dmmc_check_status(regs, &mmcstatus, status_rdy,
				status_err);
		if (err)
			return err;

		if (data->flags == MMC_DATA_READ) {
			/*
			 * MMC controller sets the Data receive ready bit
			 * (DRRDY) in MMCST0 even before the entire FIFO is
			 * full. This results in erratic behavior if we start
			 * reading the FIFO soon after DRRDY.  Wait for the
			 * FIFO full bit in MMCST1 for proper FIFO clearing.
			 */
			if (bytes_left > fifo_bytes)
				dmmc_wait_fifo_status(regs, 0x4a);
			else if (bytes_left == fifo_bytes) {
				dmmc_wait_fifo_status(regs, 0x40);
				if (cmd->cmdidx == MMC_CMD_SEND_EXT_CSD)
					udelay(600);
			}

			for (i = 0; bytes_left && (i < fifo_words); i++) {
				cmddata = get_val(&regs->mmcdrr);
				memcpy(data_buf, (char *)&cmddata, 4);
				data_buf += 4;
				bytes_left -= 4;
			}
		} else {
			/*
			 * MMC controller sets the Data transmit ready bit
			 * (DXRDY) in MMCST0 even before the entire FIFO is
			 * empty. This results in erratic behavior if we start
			 * writing the FIFO soon after DXRDY.  Wait for the
			 * FIFO empty bit in MMCST1 for proper FIFO clearing.
			 */
			dmmc_wait_fifo_status(regs, MMCST1_FIFOEMP);
			for (i = 0; bytes_left && (i < fifo_words); i++) {
				memcpy((char *)&cmddata, data_buf, 4);
				set_val(&regs->mmcdxr, cmddata);
				data_buf += 4;
				bytes_left -= 4;
			}
			dmmc_busy_wait(regs);
		}
	}

	err = dmmc_check_status(regs, &mmcstatus, MMCST0_DATDNE, status_err);
	if (err)
		return err;

	return 0;
}

/* Initialize Davinci MMC controller */
#if !CONFIG_IS_ENABLED(DM_MMC)
static int dmmc_init(struct mmc *mmc)
{
	struct davinci_mmc *host = mmc->priv;
#else
static int davinci_dm_mmc_init(struct udevice *dev)
{
	struct davinci_mmc_priv *host = dev_get_priv(dev);
#endif
	struct davinci_mmc_regs *regs = host->reg_base;

	/* Clear status registers explicitly - soft reset doesn't clear it
	 * If Uboot is invoked from UBL with SDMMC Support, the status
	 * registers can have uncleared bits
	 */
	get_val(&regs->mmcst0);
	get_val(&regs->mmcst1);

	/* Hold software reset */
	set_bit(&regs->mmcctl, MMCCTL_DATRST);
	set_bit(&regs->mmcctl, MMCCTL_CMDRST);
	udelay(10);

	set_val(&regs->mmcclk, 0x0);
	set_val(&regs->mmctor, 0x1FFF);
	set_val(&regs->mmctod, 0xFFFF);

	/* Clear software reset */
	clear_bit(&regs->mmcctl, MMCCTL_DATRST);
	clear_bit(&regs->mmcctl, MMCCTL_CMDRST);

	udelay(10);

	/* Reset FIFO - Always use the maximum fifo threshold */
	set_val(&regs->mmcfifoctl, (MMCFIFOCTL_FIFOLEV | MMCFIFOCTL_FIFORST));
	set_val(&regs->mmcfifoctl, MMCFIFOCTL_FIFOLEV);

	return 0;
}

/* Set buswidth or clock as indicated by the MMC framework */
#if !CONFIG_IS_ENABLED(DM_MMC)
static int dmmc_set_ios(struct mmc *mmc)
{
	struct davinci_mmc *host = mmc->priv;
	struct davinci_mmc_regs *regs = host->reg_base;
#else
static int davinci_mmc_set_ios(struct udevice *dev)
{
	struct mmc *mmc = mmc_get_mmc_dev(dev);

	struct davinci_mmc_priv *host = dev_get_priv(dev);
	struct davinci_mmc_regs *regs = host->reg_base;
#endif
	/* Set the bus width */
	if (mmc->bus_width == 4)
		set_bit(&regs->mmcctl, MMCCTL_WIDTH_4_BIT);
	else
		clear_bit(&regs->mmcctl, MMCCTL_WIDTH_4_BIT);

	/* Set clock speed */
	if (mmc->clock) {
#if !CONFIG_IS_ENABLED(DM_MMC)
		dmmc_set_clock(mmc, mmc->clock);
#else
		davinci_mmc_set_clock(dev, mmc->clock);
#endif
	}
	return 0;
}

#if !CONFIG_IS_ENABLED(DM_MMC)
static const struct mmc_ops dmmc_ops = {
       .send_cmd       = dmmc_send_cmd,
       .set_ios        = dmmc_set_ios,
       .init           = dmmc_init,
};
#else

static int davinci_mmc_getcd(struct udevice *dev)
{
	int value = -1;
#if CONFIG_IS_ENABLED(DM_GPIO)
	struct davinci_mmc_priv *priv = dev_get_priv(dev);
	value = dm_gpio_get_value(&priv->cd_gpio);
#endif
	/* if no CD return as 1 */
	if (value < 0)
		return 1;

	return value;
}

static int davinci_mmc_getwp(struct udevice *dev)
{
	int value = -1;
#if CONFIG_IS_ENABLED(DM_GPIO)
	struct davinci_mmc_priv *priv = dev_get_priv(dev);

	value = dm_gpio_get_value(&priv->wp_gpio);
#endif
	/* if no WP return as 0 */
	if (value < 0)
		return 0;

	return value;
}

static const struct dm_mmc_ops davinci_mmc_ops = {
	.send_cmd	= davinci_mmc_send_cmd,
	.set_ios	= davinci_mmc_set_ios,
	.get_cd		= davinci_mmc_getcd,
	.get_wp		= davinci_mmc_getwp,
};
#endif

#if !CONFIG_IS_ENABLED(DM_MMC)
/* Called from board_mmc_init during startup. Can be called multiple times
* depending on the number of slots available on board and controller
*/
int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host)
{
	host->cfg.name = "davinci";
	host->cfg.ops = &dmmc_ops;
	host->cfg.f_min = 200000;
	host->cfg.f_max = 25000000;
	host->cfg.voltages = host->voltages;
	host->cfg.host_caps = host->host_caps;

	host->cfg.b_max = DAVINCI_MAX_BLOCKS;

	mmc_create(&host->cfg, host);

	return 0;
}
#else


static int davinci_mmc_probe(struct udevice *dev)
{
	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
	struct davinci_mmc_plat *plat = dev_get_platdata(dev);
	struct davinci_mmc_priv *priv = dev_get_priv(dev);
 	struct mmc_config *cfg = &plat->cfg;
#ifdef CONFIG_SPL_BUILD
	int ret;
#endif

	cfg->f_min = 200000;
	cfg->f_max = 25000000;
	cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
	cfg->host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */
	cfg->b_max = DAVINCI_MAX_BLOCKS;
	cfg->name = "da830-mmc";

	priv->reg_base = (struct davinci_mmc_regs *)dev_read_addr(dev);
	priv->input_clk = clk_get(DAVINCI_MMCSD_CLKID);

#if CONFIG_IS_ENABLED(DM_GPIO)
	/* These GPIOs are optional */
	gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
	gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
#endif

	upriv->mmc = &plat->mmc;

#ifdef CONFIG_SPL_BUILD
	/*
	 * FIXME This is a temporary workaround to enable the driver model in
	 * SPL on omapl138-lcdk. For some reason the bind() callback is not
	 * being called in SPL for MMC which breaks the mmc boot - the hack
	 * is to call mmc_bind() from probe(). We also don't have full DT
	 * support in SPL, hence the hard-coded base register address.
	 */
	priv->reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE;
	ret = mmc_bind(dev, &plat->mmc, &plat->cfg);
	if (ret)
		return ret;
#endif

	return davinci_dm_mmc_init(dev);
}

static int davinci_mmc_bind(struct udevice *dev)
{
	struct davinci_mmc_plat *plat = dev_get_platdata(dev);

	return mmc_bind(dev, &plat->mmc, &plat->cfg);
}

static const struct udevice_id davinci_mmc_ids[] = {
	{ .compatible = "ti,da830-mmc" },
	{},
};

U_BOOT_DRIVER(davinci_mmc_drv) = {
	.name = "davinci_mmc",
	.id		= UCLASS_MMC,
	.of_match	= davinci_mmc_ids,
#if CONFIG_BLK
	.bind		= davinci_mmc_bind,
#endif
	.probe = davinci_mmc_probe,
	.ops = &davinci_mmc_ops,
	.platdata_auto_alloc_size = sizeof(struct davinci_mmc_plat),
	.priv_auto_alloc_size = sizeof(struct davinci_mmc_priv),
};
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
57418d21 SP	2	/*
	3	* Davinci MMC Controller Driver
	4	*
	5	* Copyright (C) 2010 Texas Instruments Incorporated
57418d21 SP	6	*/
	7
	8	#include <config.h>
	9	#include <common.h>
df6565c3	10	#include <dm.h>
915ffa52	11	#include <errno.h>
57418d21	12	#include <mmc.h>
df6565c3	13	#include <command.h>
57418d21 SP	14	#include <part.h>
	15	#include <malloc.h>
	16	#include <asm/io.h>
	17	#include <asm/arch/sdmmc_defs.h>
04355de7	18	#include <asm-generic/gpio.h>
57418d21 SP	19
	20	#define DAVINCI_MAX_BLOCKS (32)
	21	#define WATCHDOG_COUNT (100000)
	22
	23	#define get_val(addr) REG(addr)
	24	#define set_val(addr, val) REG(addr) = (val)
	25	#define set_bit(addr, val) set_val((addr), (get_val(addr) \| (val)))
	26	#define clear_bit(addr, val) set_val((addr), (get_val(addr) & ~(val)))
	27
df6565c3	28	#ifdef CONFIG_DM_MMC
df6565c3 AF	29	/* Davinci MMC board definitions */
	30	struct davinci_mmc_priv {
	31	struct davinci_mmc_regs reg_base; / Register base address */
	32	uint input_clk; /* Input clock to MMC controller */
04355de7 AF	33	struct gpio_desc cd_gpio; /* Card Detect GPIO */
04355de7 AF	34	struct gpio_desc wp_gpio; /* Write Protect GPIO */
797eee36 TR	35	};
	36
	37	struct davinci_mmc_plat
	38	{
df6565c3 AF	39	struct mmc_config cfg;
	40	struct mmc mmc;
	41	};
	42	#endif
	43
57418d21	44	/* Set davinci clock prescalar value based on the required clock in HZ */
df6565c3	45	#if !CONFIG_IS_ENABLED(DM_MMC)
57418d21 SP	46	static void dmmc_set_clock(struct mmc *mmc, uint clock)
	47	{
	48	struct davinci_mmc *host = mmc->priv;
df6565c3 AF	49	#else
	50
	51	static void davinci_mmc_set_clock(struct udevice *dev, uint clock)
	52	{
	53	struct davinci_mmc_priv *host = dev_get_priv(dev);
	54	struct mmc *mmc = mmc_get_mmc_dev(dev);
	55	#endif
57418d21 SP	56	struct davinci_mmc_regs *regs = host->reg_base;
	57	uint clkrt, sysclk2, act_clock;
	58
93bfd616 PA	59	if (clock < mmc->cfg->f_min)
	60	clock = mmc->cfg->f_min;
	61	if (clock > mmc->cfg->f_max)
	62	clock = mmc->cfg->f_max;
57418d21 SP	63
	64	set_val(&regs->mmcclk, 0);
	65	sysclk2 = host->input_clk;
	66	clkrt = (sysclk2 / (2 * clock)) - 1;
	67
	68	/* Calculate the actual clock for the divider used */
	69	act_clock = (sysclk2 / (2 * (clkrt + 1)));
	70
	71	/* Adjust divider if actual clock exceeds the required clock */
	72	if (act_clock > clock)
	73	clkrt++;
	74
	75	/* check clock divider boundary and correct it */
	76	if (clkrt > 0xFF)
	77	clkrt = 0xFF;
	78
	79	set_val(&regs->mmcclk, (clkrt \| MMCCLK_CLKEN));
	80	}
	81
	82	/* Status bit wait loop for MMCST1 */
	83	static int
	84	dmmc_wait_fifo_status(volatile struct davinci_mmc_regs *regs, uint status)
	85	{
79b05d59 HS	86	uint wdog = WATCHDOG_COUNT;
79b05d59 HS	87
57418d21 SP	88	while (--wdog && ((get_val(&regs->mmcst1) & status) != status))
	89	udelay(10);
	90
	91	if (!(get_val(&regs->mmcctl) & MMCCTL_WIDTH_4_BIT))
	92	udelay(100);
	93
	94	if (wdog == 0)
915ffa52	95	return -ECOMM;
57418d21 SP	96
	97	return 0;
	98	}
	99
	100	/* Busy bit wait loop for MMCST1 */
	101	static int dmmc_busy_wait(volatile struct davinci_mmc_regs *regs)
	102	{
79b05d59	103	uint wdog = WATCHDOG_COUNT;
57418d21	104
57418d21 SP	105	while (--wdog && (get_val(&regs->mmcst1) & MMCST1_BUSY))
	106	udelay(10);
	107
	108	if (wdog == 0)
915ffa52	109	return -ECOMM;
57418d21 SP	110
	111	return 0;
	112	}
	113
	114	/* Status bit wait loop for MMCST0 - Checks for error bits as well */
	115	static int dmmc_check_status(volatile struct davinci_mmc_regs *regs,
	116	uint *cur_st, uint st_ready, uint st_error)
	117	{
	118	uint wdog = WATCHDOG_COUNT;
	119	uint mmcstatus = *cur_st;
	120
	121	while (wdog--) {
	122	if (mmcstatus & st_ready) {
	123	*cur_st = mmcstatus;
	124	mmcstatus = get_val(&regs->mmcst1);
	125	return 0;
	126	} else if (mmcstatus & st_error) {
	127	if (mmcstatus & MMCST0_TOUTRS)
915ffa52	128	return -ETIMEDOUT;
57418d21 SP	129	printf("[ ST0 ERROR %x]\n", mmcstatus);
	130	/*
	131	* Ignore CRC errors as some MMC cards fail to
	132	* initialize on DM365-EVM on the SD1 slot
	133	*/
	134	if (mmcstatus & MMCST0_CRCRS)
	135	return 0;
915ffa52	136	return -ECOMM;
57418d21 SP	137	}
	138	udelay(10);
	139
	140	mmcstatus = get_val(&regs->mmcst0);
	141	}
	142
	143	printf("Status %x Timeout ST0:%x ST1:%x\n", st_ready, mmcstatus,
	144	get_val(&regs->mmcst1));
915ffa52	145	return -ECOMM;
57418d21 SP	146	}
	147
	148	/*
df6565c3	149	* Sends a command out on the bus. Takes the device pointer,
57418d21 SP	150	* a command pointer, and an optional data pointer.
57418d21 SP	151	*/
df6565c3 AF	152	#if !CONFIG_IS_ENABLED(DM_MMC)
df6565c3 AF	153	static int dmmc_send_cmd(struct mmc mmc, struct mmc_cmd cmd, struct mmc_data *data)
57418d21 SP	154	{
57418d21 SP	155	struct davinci_mmc *host = mmc->priv;
df6565c3 AF	156	#else
	157	static int
	158	davinci_mmc_send_cmd(struct udevice dev, struct mmc_cmd cmd, struct mmc_data *data)
	159	{
	160	struct davinci_mmc_priv *host = dev_get_priv(dev);
	161	#endif
57418d21 SP	162	volatile struct davinci_mmc_regs *regs = host->reg_base;
	163	uint mmcstatus, status_rdy, status_err;
	164	uint i, cmddata, bytes_left = 0;
	165	int fifo_words, fifo_bytes, err;
	166	char *data_buf = NULL;
	167
	168	/* Clear status registers */
	169	mmcstatus = get_val(&regs->mmcst0);
6a97153c	170	fifo_words = 16;
57418d21 SP	171	fifo_bytes = fifo_words << 2;
	172
	173	/* Wait for any previous busy signal to be cleared */
	174	dmmc_busy_wait(regs);
	175
	176	cmddata = cmd->cmdidx;
	177	cmddata \|= MMCCMD_PPLEN;
	178
	179	/* Send init clock for CMD0 */
	180	if (cmd->cmdidx == MMC_CMD_GO_IDLE_STATE)
	181	cmddata \|= MMCCMD_INITCK;
	182
	183	switch (cmd->resp_type) {
	184	case MMC_RSP_R1b:
	185	cmddata \|= MMCCMD_BSYEXP;
	186	/* Fall-through */
	187	case MMC_RSP_R1: /* R1, R1b, R5, R6, R7 */
	188	cmddata \|= MMCCMD_RSPFMT_R1567;
	189	break;
	190	case MMC_RSP_R2:
	191	cmddata \|= MMCCMD_RSPFMT_R2;
	192	break;
	193	case MMC_RSP_R3: /* R3, R4 */
	194	cmddata \|= MMCCMD_RSPFMT_R3;
	195	break;
	196	}
	197
	198	set_val(&regs->mmcim, 0);
	199
	200	if (data) {
	201	/* clear previous data transfer if any and set new one */
	202	bytes_left = (data->blocksize * data->blocks);
	203
	204	/* Reset FIFO - Always use 32 byte fifo threshold */
	205	set_val(&regs->mmcfifoctl,
	206	(MMCFIFOCTL_FIFOLEV \| MMCFIFOCTL_FIFORST));
	207
6a97153c	208	cmddata \|= MMCCMD_DMATRIG;
57418d21 SP	209
	210	cmddata \|= MMCCMD_WDATX;
	211	if (data->flags == MMC_DATA_READ) {
	212	set_val(&regs->mmcfifoctl, MMCFIFOCTL_FIFOLEV);
	213	} else if (data->flags == MMC_DATA_WRITE) {
	214	set_val(&regs->mmcfifoctl,
	215	(MMCFIFOCTL_FIFOLEV \|
	216	MMCFIFOCTL_FIFODIR));
	217	cmddata \|= MMCCMD_DTRW;
	218	}
	219
	220	set_val(&regs->mmctod, 0xFFFF);
	221	set_val(&regs->mmcnblk, (data->blocks & MMCNBLK_NBLK_MASK));
	222	set_val(&regs->mmcblen, (data->blocksize & MMCBLEN_BLEN_MASK));
	223
	224	if (data->flags == MMC_DATA_WRITE) {
	225	uint val;
	226	data_buf = (char *)data->src;
	227	/* For write, fill FIFO with data before issue of CMD */
	228	for (i = 0; (i < fifo_words) && bytes_left; i++) {
	229	memcpy((char *)&val, data_buf, 4);
	230	set_val(&regs->mmcdxr, val);
	231	data_buf += 4;
	232	bytes_left -= 4;
	233	}
	234	}
	235	} else {
	236	set_val(&regs->mmcblen, 0);
	237	set_val(&regs->mmcnblk, 0);
	238	}
	239
	240	set_val(&regs->mmctor, 0x1FFF);
	241
	242	/* Send the command */
	243	set_val(&regs->mmcarghl, cmd->cmdarg);
	244	set_val(&regs->mmccmd, cmddata);
	245
	246	status_rdy = MMCST0_RSPDNE;
	247	status_err = (MMCST0_TOUTRS \| MMCST0_TOUTRD \|
	248	MMCST0_CRCWR \| MMCST0_CRCRD);
	249	if (cmd->resp_type & MMC_RSP_CRC)
	250	status_err \|= MMCST0_CRCRS;
	251
	252	mmcstatus = get_val(&regs->mmcst0);
	253	err = dmmc_check_status(regs, &mmcstatus, status_rdy, status_err);
	254	if (err)
	255	return err;
	256
	257	/* For R1b wait for busy done */
	258	if (cmd->resp_type == MMC_RSP_R1b)
	259	dmmc_busy_wait(regs);
	260
	261	/* Collect response from controller for specific commands */
	262	if (mmcstatus & MMCST0_RSPDNE) {
	263	/* Copy the response to the response buffer */
	264	if (cmd->resp_type & MMC_RSP_136) {
	265	cmd->response[0] = get_val(&regs->mmcrsp67);
	266	cmd->response[1] = get_val(&regs->mmcrsp45);
	267	cmd->response[2] = get_val(&regs->mmcrsp23);
	268	cmd->response[3] = get_val(&regs->mmcrsp01);
	269	} else if (cmd->resp_type & MMC_RSP_PRESENT) {
	270	cmd->response[0] = get_val(&regs->mmcrsp67);
	271	}
	272	}
273
274	if (data == NULL)
275	return 0;
276
277	if (data->flags == MMC_DATA_READ) {
278	/* check for DATDNE along with DRRDY as the controller might
279	* set the DATDNE without DRRDY for smaller transfers with
280	* less than FIFO threshold bytes
281	*/
282	status_rdy = MMCST0_DRRDY \| MMCST0_DATDNE;
283	status_err = MMCST0_TOUTRD \| MMCST0_CRCRD;
284	data_buf = data->dest;
285	} else {
286	status_rdy = MMCST0_DXRDY \| MMCST0_DATDNE;
287	status_err = MMCST0_CRCWR;
288	}
289
290	/* Wait until all of the blocks are transferred */
291	while (bytes_left) {
292	err = dmmc_check_status(regs, &mmcstatus, status_rdy,
293	status_err);
294	if (err)
295	return err;
296
297	if (data->flags == MMC_DATA_READ) {
298	/*
299	* MMC controller sets the Data receive ready bit
300	* (DRRDY) in MMCST0 even before the entire FIFO is
301	* full. This results in erratic behavior if we start
302	* reading the FIFO soon after DRRDY. Wait for the
303	* FIFO full bit in MMCST1 for proper FIFO clearing.
304	*/
305	if (bytes_left > fifo_bytes)
306	dmmc_wait_fifo_status(regs, 0x4a);
3ba36d60	307	else if (bytes_left == fifo_bytes) {
57418d21	308	dmmc_wait_fifo_status(regs, 0x40);
3ba36d60 DB	309	if (cmd->cmdidx == MMC_CMD_SEND_EXT_CSD)
	310	udelay(600);
	311	}
57418d21 SP	312
	313	for (i = 0; bytes_left && (i < fifo_words); i++) {
	314	cmddata = get_val(&regs->mmcdrr);
	315	memcpy(data_buf, (char *)&cmddata, 4);
	316	data_buf += 4;
	317	bytes_left -= 4;
	318	}
	319	} else {
	320	/*
	321	* MMC controller sets the Data transmit ready bit
	322	* (DXRDY) in MMCST0 even before the entire FIFO is
	323	* empty. This results in erratic behavior if we start
	324	* writing the FIFO soon after DXRDY. Wait for the
	325	* FIFO empty bit in MMCST1 for proper FIFO clearing.
	326	*/
	327	dmmc_wait_fifo_status(regs, MMCST1_FIFOEMP);
	328	for (i = 0; bytes_left && (i < fifo_words); i++) {
	329	memcpy((char *)&cmddata, data_buf, 4);
	330	set_val(&regs->mmcdxr, cmddata);
	331	data_buf += 4;
	332	bytes_left -= 4;
	333	}
	334	dmmc_busy_wait(regs);
	335	}
	336	}
	337
	338	err = dmmc_check_status(regs, &mmcstatus, MMCST0_DATDNE, status_err);
	339	if (err)
	340	return err;
	341
	342	return 0;
	343	}
	344
	345	/* Initialize Davinci MMC controller */
df6565c3	346	#if !CONFIG_IS_ENABLED(DM_MMC)
57418d21 SP	347	static int dmmc_init(struct mmc *mmc)
	348	{
	349	struct davinci_mmc *host = mmc->priv;
df6565c3 AF	350	#else
	351	static int davinci_dm_mmc_init(struct udevice *dev)
	352	{
	353	struct davinci_mmc_priv *host = dev_get_priv(dev);
	354	#endif
57418d21 SP	355	struct davinci_mmc_regs *regs = host->reg_base;
	356
	357	/* Clear status registers explicitly - soft reset doesn't clear it
	358	* If Uboot is invoked from UBL with SDMMC Support, the status
	359	* registers can have uncleared bits
	360	*/
	361	get_val(&regs->mmcst0);
	362	get_val(&regs->mmcst1);
	363
	364	/* Hold software reset */
	365	set_bit(&regs->mmcctl, MMCCTL_DATRST);
	366	set_bit(&regs->mmcctl, MMCCTL_CMDRST);
	367	udelay(10);
	368
	369	set_val(&regs->mmcclk, 0x0);
	370	set_val(&regs->mmctor, 0x1FFF);
	371	set_val(&regs->mmctod, 0xFFFF);
	372
	373	/* Clear software reset */
	374	clear_bit(&regs->mmcctl, MMCCTL_DATRST);
	375	clear_bit(&regs->mmcctl, MMCCTL_CMDRST);
	376
	377	udelay(10);
	378
	379	/* Reset FIFO - Always use the maximum fifo threshold */
	380	set_val(&regs->mmcfifoctl, (MMCFIFOCTL_FIFOLEV \| MMCFIFOCTL_FIFORST));
	381	set_val(&regs->mmcfifoctl, MMCFIFOCTL_FIFOLEV);
	382
	383	return 0;
	384	}
	385
4aa2ba3a	386	/* Set buswidth or clock as indicated by the MMC framework */
df6565c3	387	#if !CONFIG_IS_ENABLED(DM_MMC)
07b0b9c0	388	static int dmmc_set_ios(struct mmc *mmc)
57418d21 SP	389	{
	390	struct davinci_mmc *host = mmc->priv;
	391	struct davinci_mmc_regs *regs = host->reg_base;
df6565c3 AF	392	#else
	393	static int davinci_mmc_set_ios(struct udevice *dev)
	394	{
	395	struct mmc *mmc = mmc_get_mmc_dev(dev);
57418d21	396
df6565c3 AF	397	struct davinci_mmc_priv *host = dev_get_priv(dev);
	398	struct davinci_mmc_regs *regs = host->reg_base;
	399	#endif
57418d21 SP	400	/* Set the bus width */
	401	if (mmc->bus_width == 4)
	402	set_bit(&regs->mmcctl, MMCCTL_WIDTH_4_BIT);
	403	else
	404	clear_bit(&regs->mmcctl, MMCCTL_WIDTH_4_BIT);
	405
	406	/* Set clock speed */
df6565c3 AF	407	if (mmc->clock) {
df6565c3 AF	408	#if !CONFIG_IS_ENABLED(DM_MMC)
57418d21	409	dmmc_set_clock(mmc, mmc->clock);
df6565c3 AF	410	#else
	411	davinci_mmc_set_clock(dev, mmc->clock);
	412	#endif
	413	}
07b0b9c0	414	return 0;
57418d21 SP	415	}
57418d21 SP	416
df6565c3	417	#if !CONFIG_IS_ENABLED(DM_MMC)
ab769f22	418	static const struct mmc_ops dmmc_ops = {
df6565c3 AF	419	.send_cmd = dmmc_send_cmd,
	420	.set_ios = dmmc_set_ios,
	421	.init = dmmc_init,
ab769f22	422	};
df6565c3	423	#else
04355de7 AF	424
	425	static int davinci_mmc_getcd(struct udevice *dev)
	426	{
	427	int value = -1;
	428	#if CONFIG_IS_ENABLED(DM_GPIO)
	429	struct davinci_mmc_priv *priv = dev_get_priv(dev);
	430	value = dm_gpio_get_value(&priv->cd_gpio);
	431	#endif
	432	/* if no CD return as 1 */
	433	if (value < 0)
	434	return 1;
	435
	436	return value;
	437	}
	438
	439	static int davinci_mmc_getwp(struct udevice *dev)
	440	{
	441	int value = -1;
	442	#if CONFIG_IS_ENABLED(DM_GPIO)
	443	struct davinci_mmc_priv *priv = dev_get_priv(dev);
	444
	445	value = dm_gpio_get_value(&priv->wp_gpio);
	446	#endif
	447	/* if no WP return as 0 */
	448	if (value < 0)
	449	return 0;
	450
	451	return value;
	452	}
	453
df6565c3 AF	454	static const struct dm_mmc_ops davinci_mmc_ops = {
	455	.send_cmd = davinci_mmc_send_cmd,
	456	.set_ios = davinci_mmc_set_ios,
04355de7 AF	457	.get_cd = davinci_mmc_getcd,
04355de7 AF	458	.get_wp = davinci_mmc_getwp,
df6565c3 AF	459	};
df6565c3 AF	460	#endif
ab769f22	461
df6565c3	462	#if !CONFIG_IS_ENABLED(DM_MMC)
57418d21	463	/* Called from board_mmc_init during startup. Can be called multiple times
df6565c3 AF	464	* depending on the number of slots available on board and controller
df6565c3 AF	465	*/
57418d21 SP	466	int davinci_mmc_init(bd_t bis, struct davinci_mmc host)
57418d21 SP	467	{
93bfd616 PA	468	host->cfg.name = "davinci";
	469	host->cfg.ops = &dmmc_ops;
	470	host->cfg.f_min = 200000;
	471	host->cfg.f_max = 25000000;
	472	host->cfg.voltages = host->voltages;
	473	host->cfg.host_caps = host->host_caps;
57418d21	474
93bfd616	475	host->cfg.b_max = DAVINCI_MAX_BLOCKS;
57418d21	476
93bfd616	477	mmc_create(&host->cfg, host);
57418d21 SP	478
	479	return 0;
	480	}
df6565c3 AF	481	#else
	482
	483
	484	static int davinci_mmc_probe(struct udevice *dev)
	485	{
	486	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
797eee36	487	struct davinci_mmc_plat *plat = dev_get_platdata(dev);
df6565c3	488	struct davinci_mmc_priv *priv = dev_get_priv(dev);
797eee36	489	struct mmc_config *cfg = &plat->cfg;
3ef94715 BG	490	#ifdef CONFIG_SPL_BUILD
	491	int ret;
	492	#endif
6a97153c	493
df6565c3 AF	494	cfg->f_min = 200000;
	495	cfg->f_max = 25000000;
	496	cfg->voltages = MMC_VDD_32_33 \| MMC_VDD_33_34,
	497	cfg->host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */
	498	cfg->b_max = DAVINCI_MAX_BLOCKS;
6a97153c	499	cfg->name = "da830-mmc";
df6565c3 AF	500
	501	priv->reg_base = (struct davinci_mmc_regs *)dev_read_addr(dev);
	502	priv->input_clk = clk_get(DAVINCI_MMCSD_CLKID);
	503
04355de7 AF	504	#if CONFIG_IS_ENABLED(DM_GPIO)
	505	/* These GPIOs are optional */
	506	gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
	507	gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
	508	#endif
	509
797eee36	510	upriv->mmc = &plat->mmc;
df6565c3	511
3ef94715 BG	512	#ifdef CONFIG_SPL_BUILD
	513	/*
	514	* FIXME This is a temporary workaround to enable the driver model in
	515	* SPL on omapl138-lcdk. For some reason the bind() callback is not
	516	* being called in SPL for MMC which breaks the mmc boot - the hack
	517	* is to call mmc_bind() from probe(). We also don't have full DT
	518	* support in SPL, hence the hard-coded base register address.
	519	*/
	520	priv->reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE;
797eee36	521	ret = mmc_bind(dev, &plat->mmc, &plat->cfg);
3ef94715 BG	522	if (ret)
	523	return ret;
	524	#endif
	525
df6565c3 AF	526	return davinci_dm_mmc_init(dev);
	527	}
	528
	529	static int davinci_mmc_bind(struct udevice *dev)
	530	{
797eee36	531	struct davinci_mmc_plat *plat = dev_get_platdata(dev);
df6565c3	532
797eee36	533	return mmc_bind(dev, &plat->mmc, &plat->cfg);
df6565c3 AF	534	}
df6565c3 AF	535
df6565c3	536	static const struct udevice_id davinci_mmc_ids[] = {
6a97153c	537	{ .compatible = "ti,da830-mmc" },
df6565c3 AF	538	{},
	539	};
	540
	541	U_BOOT_DRIVER(davinci_mmc_drv) = {
	542	.name = "davinci_mmc",
	543	.id = UCLASS_MMC,
	544	.of_match = davinci_mmc_ids,
	545	#if CONFIG_BLK
	546	.bind = davinci_mmc_bind,
	547	#endif
	548	.probe = davinci_mmc_probe,
	549	.ops = &davinci_mmc_ops,
797eee36	550	.platdata_auto_alloc_size = sizeof(struct davinci_mmc_plat),
df6565c3 AF	551	.priv_auto_alloc_size = sizeof(struct davinci_mmc_priv),
	552	};
	553	#endif