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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
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2 | /* |
3 | * Copyright (C) 2007-2013 Tensilica, Inc. | |
4 | * Copyright (C) 2014 - 2016 Cadence Design Systems Inc. | |
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5 | */ |
6 | ||
7 | #ifndef __CONFIG_H | |
8 | #define __CONFIG_H | |
9 | ||
10 | #include <asm/arch/core.h> | |
11 | #include <asm/addrspace.h> | |
12 | #include <asm/config.h> | |
13 | ||
14 | /* | |
15 | * The 'xtfpga' board describes a set of very similar boards with only minimal | |
16 | * differences. | |
17 | */ | |
18 | ||
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19 | /*===================*/ |
20 | /* RAM Layout */ | |
21 | /*===================*/ | |
22 | ||
23 | #if XCHAL_HAVE_PTP_MMU | |
24 | #define CONFIG_SYS_MEMORY_BASE \ | |
25 | (XCHAL_VECBASE_RESET_VADDR - XCHAL_VECBASE_RESET_PADDR) | |
26 | #define CONFIG_SYS_IO_BASE 0xf0000000 | |
27 | #else | |
28 | #define CONFIG_SYS_MEMORY_BASE 0x60000000 | |
29 | #define CONFIG_SYS_IO_BASE 0x90000000 | |
30 | #define CONFIG_MAX_MEM_MAPPED 0x10000000 | |
31 | #endif | |
32 | ||
33 | /* Onboard RAM sizes: | |
34 | * | |
35 | * LX60 0x04000000 64 MB | |
36 | * LX110 0x03000000 48 MB | |
37 | * LX200 0x06000000 96 MB | |
38 | * ML605 0x18000000 384 MB | |
39 | * KC705 0x38000000 896 MB | |
40 | * | |
41 | * noMMU configurations can only see first 256MB of onboard memory. | |
42 | */ | |
43 | ||
44 | #if XCHAL_HAVE_PTP_MMU || CONFIG_BOARD_SDRAM_SIZE < 0x10000000 | |
45 | #define CONFIG_SYS_SDRAM_SIZE CONFIG_BOARD_SDRAM_SIZE | |
46 | #else | |
47 | #define CONFIG_SYS_SDRAM_SIZE 0x10000000 | |
48 | #endif | |
49 | ||
50 | #define CONFIG_SYS_SDRAM_BASE MEMADDR(0x00000000) | |
51 | ||
52 | /* Lx60 can only map 128kb memory (instead of 256kb) when running under OCD */ | |
7e270ec3 | 53 | |
7e270ec3 | 54 | /* Memory test is destructive so default must not overlap vectors or U-Boot*/ |
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55 | |
56 | /* Load address for stand-alone applications. | |
57 | * MEMADDR cannot be used here, because the definition needs to be | |
58 | * a plain number as it's used as -Ttext argument for ld in standalone | |
59 | * example makefile. | |
60 | * Handle noMMU vs MMUv2 vs MMUv3 distinction here manually. | |
61 | */ | |
62 | #if XCHAL_HAVE_PTP_MMU | |
63 | #if XCHAL_VECBASE_RESET_VADDR == XCHAL_VECBASE_RESET_PADDR | |
64 | #define CONFIG_STANDALONE_LOAD_ADDR 0x00800000 | |
65 | #else | |
66 | #define CONFIG_STANDALONE_LOAD_ADDR 0xd0800000 | |
67 | #endif | |
68 | #else | |
69 | #define CONFIG_STANDALONE_LOAD_ADDR 0x60800000 | |
70 | #endif | |
71 | ||
72 | #if defined(CONFIG_MAX_MEM_MAPPED) && \ | |
73 | CONFIG_MAX_MEM_MAPPED < CONFIG_SYS_SDRAM_SIZE | |
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74 | #define XTENSA_SYS_TEXT_ADDR \ |
75 | (MEMADDR(CONFIG_MAX_MEM_MAPPED) - CONFIG_SYS_MONITOR_LEN) | |
7e270ec3 | 76 | #else |
10117a29 | 77 | #define XTENSA_SYS_TEXT_ADDR \ |
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78 | (MEMADDR(CONFIG_SYS_SDRAM_SIZE) - CONFIG_SYS_MONITOR_LEN) |
79 | #endif | |
7e270ec3 | 80 | |
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81 | /*==============================*/ |
82 | /* U-Boot general configuration */ | |
83 | /*==============================*/ | |
84 | ||
7e270ec3 | 85 | /* Console I/O Buffer Size */ |
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86 | /*==============================*/ |
87 | /* U-Boot autoboot configuration */ | |
88 | /*==============================*/ | |
89 | ||
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90 | |
91 | /*=========================================*/ | |
92 | /* FPGA Registers (board info and control) */ | |
93 | /*=========================================*/ | |
94 | ||
95 | /* | |
96 | * These assume FPGA bitstreams from Tensilica release RB and up. Earlier | |
97 | * releases may not provide any/all of these registers or at these offsets. | |
98 | * Some of the FPGA registers are broken down into bitfields described by | |
99 | * SHIFT left amount and field WIDTH (bits), and also by a bitMASK. | |
100 | */ | |
101 | ||
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102 | /* FPGA core clock frequency in Hz (also input to UART) */ |
103 | #define CONFIG_SYS_FPGAREG_FREQ IOADDR(0x0D020004) /* CPU clock frequency*/ | |
104 | ||
105 | /* | |
106 | * DIP switch (left=sw1=lsb=bit0, right=sw8=msb=bit7; off=0, on=1): | |
107 | * Bits 0..5 set the lower 6 bits of the default ethernet MAC. | |
108 | * Bit 6 is reserved for future use by Tensilica. | |
109 | * Bit 7 maps the first 128KB of ROM address space at CONFIG_SYS_ROM_BASE to | |
110 | * the base of flash * (when on/1) or to the base of RAM (when off/0). | |
111 | */ | |
112 | #define CONFIG_SYS_FPGAREG_DIPSW IOADDR(0x0D02000C) | |
113 | #define FPGAREG_MAC_SHIFT 0 /* Ethernet MAC bits 0..5 */ | |
114 | #define FPGAREG_MAC_WIDTH 6 | |
115 | #define FPGAREG_MAC_MASK 0x3f | |
116 | #define FPGAREG_BOOT_SHIFT 7 /* Boot ROM addr mapping */ | |
117 | #define FPGAREG_BOOT_WIDTH 1 | |
118 | #define FPGAREG_BOOT_MASK 0x80 | |
119 | #define FPGAREG_BOOT_RAM 0 | |
120 | #define FPGAREG_BOOT_FLASH (1<<FPGAREG_BOOT_SHIFT) | |
121 | ||
122 | /* Force hard reset of board by writing a code to this register */ | |
123 | #define CONFIG_SYS_FPGAREG_RESET IOADDR(0x0D020010) /* Reset board .. */ | |
124 | #define CONFIG_SYS_FPGAREG_RESET_CODE 0x0000DEAD /* by writing this code */ | |
125 | ||
126 | /*====================*/ | |
127 | /* Serial Driver Info */ | |
128 | /*====================*/ | |
129 | ||
130 | #define CONFIG_SYS_NS16550_SERIAL | |
131 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
132 | #define CONFIG_SYS_NS16550_COM1 IOADDR(0x0D050020) /* Base address */ | |
133 | ||
134 | /* Input clk to NS16550 (in Hz; the SYS_CLK_FREQ is in kHz) */ | |
2f8a6db5 | 135 | #define CONFIG_SYS_NS16550_CLK get_board_sys_clk() |
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136 | |
137 | /*======================*/ | |
138 | /* Ethernet Driver Info */ | |
139 | /*======================*/ | |
140 | ||
141 | #define CONFIG_ETHBASE 00:50:C2:13:6f:00 | |
142 | #define CONFIG_SYS_ETHOC_BASE IOADDR(0x0d030000) | |
143 | #define CONFIG_SYS_ETHOC_BUFFER_ADDR IOADDR(0x0D800000) | |
144 | ||
145 | /*=====================*/ | |
146 | /* Flash & Environment */ | |
147 | /*=====================*/ | |
148 | ||
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149 | #ifdef CONFIG_XTFPGA_LX60 |
150 | # define CONFIG_SYS_FLASH_SIZE 0x0040000 /* 4MB */ | |
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151 | # define CONFIG_SYS_FLASH_PARMSECT_SZ 0x2000 /* param size 8KB */ |
152 | # define CONFIG_SYS_FLASH_BASE IOADDR(0x08000000) | |
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153 | #elif defined(CONFIG_XTFPGA_KC705) |
154 | # define CONFIG_SYS_FLASH_SIZE 0x8000000 /* 128MB */ | |
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155 | # define CONFIG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */ |
156 | # define CONFIG_SYS_FLASH_BASE IOADDR(0x00000000) | |
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157 | #else |
158 | # define CONFIG_SYS_FLASH_SIZE 0x1000000 /* 16MB */ | |
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159 | # define CONFIG_SYS_FLASH_PARMSECT_SZ 0x8000 /* param size 32KB */ |
160 | # define CONFIG_SYS_FLASH_BASE IOADDR(0x08000000) | |
7e270ec3 | 161 | #endif |
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162 | |
163 | /* | |
164 | * Put environment in top block (64kB) | |
165 | * Another option would be to put env. in 2nd param block offs 8KB, size 8KB | |
166 | */ | |
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167 | |
168 | /* print 'E' for empty sector on flinfo */ | |
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169 | |
170 | #endif /* __CONFIG_H */ |