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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
c8a7d9da WH |
2 | /* |
3 | * Copyright 2014 Freescale Semiconductor, Inc. | |
b416df33 | 4 | * Copyright 2019, 2021 NXP |
c8a7d9da WH |
5 | */ |
6 | ||
7 | #ifndef __CONFIG_H | |
8 | #define __CONFIG_H | |
9 | ||
c8a7d9da WH |
10 | #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR |
11 | #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE | |
12 | ||
a88cc3bd YS |
13 | #define DDR_SDRAM_CFG 0x470c0008 |
14 | #define DDR_CS0_BNDS 0x008000bf | |
15 | #define DDR_CS0_CONFIG 0x80014302 | |
16 | #define DDR_TIMING_CFG_0 0x50550004 | |
17 | #define DDR_TIMING_CFG_1 0xbcb38c56 | |
18 | #define DDR_TIMING_CFG_2 0x0040d120 | |
19 | #define DDR_TIMING_CFG_3 0x010e1000 | |
20 | #define DDR_TIMING_CFG_4 0x00000001 | |
21 | #define DDR_TIMING_CFG_5 0x03401400 | |
22 | #define DDR_SDRAM_CFG_2 0x00401010 | |
23 | #define DDR_SDRAM_MODE 0x00061c60 | |
24 | #define DDR_SDRAM_MODE_2 0x00180000 | |
25 | #define DDR_SDRAM_INTERVAL 0x18600618 | |
26 | #define DDR_DDR_WRLVL_CNTL 0x8655f605 | |
27 | #define DDR_DDR_WRLVL_CNTL_2 0x05060607 | |
28 | #define DDR_DDR_WRLVL_CNTL_3 0x05050505 | |
29 | #define DDR_DDR_CDR1 0x80040000 | |
30 | #define DDR_DDR_CDR2 0x00000001 | |
31 | #define DDR_SDRAM_CLK_CNTL 0x02000000 | |
32 | #define DDR_DDR_ZQ_CNTL 0x89080600 | |
33 | #define DDR_CS0_CONFIG_2 0 | |
34 | #define DDR_SDRAM_CFG_MEM_EN 0x80000000 | |
99e1bd42 TY |
35 | #define SDRAM_CFG2_D_INIT 0x00000010 |
36 | #define DDR_CDR2_VREF_TRAIN_EN 0x00000080 | |
37 | #define SDRAM_CFG2_FRC_SR 0x80000000 | |
38 | #define SDRAM_CFG_BI 0x00000001 | |
a88cc3bd | 39 | |
8415bb68 | 40 | #ifdef CONFIG_SD_BOOT |
5536c3c9 | 41 | #ifdef CONFIG_NXP_ESBC |
e7e720c2 SG |
42 | /* |
43 | * HDR would be appended at end of image and copied to DDR along | |
44 | * with U-Boot image. | |
45 | */ | |
693d4c9f | 46 | #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) |
5536c3c9 | 47 | #endif /* ifdef CONFIG_NXP_ESBC */ |
8415bb68 | 48 | |
e7e720c2 SG |
49 | #ifdef CONFIG_U_BOOT_HDR_SIZE |
50 | /* | |
51 | * HDR would be appended at end of image and copied to DDR along | |
52 | * with U-Boot image. Here u-boot max. size is 512K. So if binary | |
53 | * size increases then increase this size in case of secure boot as | |
54 | * it uses raw u-boot image instead of fit image. | |
55 | */ | |
e7e720c2 | 56 | #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ |
8415bb68 AW |
57 | #endif |
58 | ||
c8a7d9da WH |
59 | #define PHYS_SDRAM 0x80000000 |
60 | #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) | |
61 | ||
62 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL | |
63 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
64 | ||
c8a7d9da WH |
65 | /* |
66 | * IFC Definitions | |
67 | */ | |
947cee11 | 68 | #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) |
c8a7d9da WH |
69 | #define CONFIG_SYS_FLASH_BASE 0x60000000 |
70 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
71 | ||
72 | #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) | |
73 | #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
74 | CSPR_PORT_SIZE_16 | \ | |
75 | CSPR_MSEL_NOR | \ | |
76 | CSPR_V) | |
77 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) | |
78 | ||
79 | /* NOR Flash Timing Params */ | |
80 | #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ | |
81 | CSOR_NOR_TRHZ_80) | |
82 | #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ | |
83 | FTIM0_NOR_TEADC(0x5) | \ | |
84 | FTIM0_NOR_TAVDS(0x0) | \ | |
85 | FTIM0_NOR_TEAHC(0x5)) | |
86 | #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ | |
87 | FTIM1_NOR_TRAD_NOR(0x1A) | \ | |
88 | FTIM1_NOR_TSEQRAD_NOR(0x13)) | |
89 | #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ | |
90 | FTIM2_NOR_TCH(0x4) | \ | |
91 | FTIM2_NOR_TWP(0x1c) | \ | |
92 | FTIM2_NOR_TWPH(0x0e)) | |
93 | #define CONFIG_SYS_NOR_FTIM3 0 | |
94 | ||
c8a7d9da WH |
95 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
96 | ||
c8a7d9da WH |
97 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } |
98 | ||
272c5265 | 99 | #define CONFIG_SYS_WRITE_SWAPPED_DATA |
d612f0ab | 100 | #endif |
c8a7d9da WH |
101 | |
102 | /* CPLD */ | |
103 | ||
104 | #define CONFIG_SYS_CPLD_BASE 0x7fb00000 | |
105 | #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE | |
106 | ||
107 | #define CONFIG_SYS_FPGA_CSPR_EXT (0x0) | |
108 | #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ | |
109 | CSPR_PORT_SIZE_8 | \ | |
110 | CSPR_MSEL_GPCM | \ | |
111 | CSPR_V) | |
112 | #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) | |
113 | #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ | |
114 | CSOR_NOR_NOR_MODE_AVD_NOR | \ | |
115 | CSOR_NOR_TRHZ_80) | |
116 | ||
117 | /* CPLD Timing parameters for IFC GPCM */ | |
118 | #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ | |
119 | FTIM0_GPCM_TEADC(0xf) | \ | |
120 | FTIM0_GPCM_TEAHC(0xf)) | |
121 | #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ | |
122 | FTIM1_GPCM_TRAD(0x3f)) | |
123 | #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ | |
124 | FTIM2_GPCM_TCH(0xf) | \ | |
125 | FTIM2_GPCM_TWP(0xff)) | |
126 | #define CONFIG_SYS_FPGA_FTIM3 0x0 | |
127 | #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT | |
128 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR | |
129 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
130 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
131 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
132 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
133 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
134 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
135 | #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT | |
136 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR | |
137 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK | |
138 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR | |
139 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0 | |
140 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1 | |
141 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2 | |
142 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3 | |
143 | ||
144 | /* | |
145 | * Serial Port | |
146 | */ | |
db48e525 | 147 | #ifndef CONFIG_LPUART |
c8a7d9da | 148 | #define CONFIG_SYS_NS16550_SERIAL |
f833cd62 | 149 | #ifndef CONFIG_DM_SERIAL |
c8a7d9da | 150 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
f833cd62 | 151 | #endif |
c8a7d9da | 152 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() |
55d53ab4 | 153 | #endif |
c8a7d9da | 154 | |
c8a7d9da WH |
155 | /* |
156 | * I2C | |
157 | */ | |
c8a7d9da | 158 | |
7c1f095a | 159 | /* GPIO */ |
7c1f095a | 160 | |
1a2826f6 XL |
161 | #define CONFIG_PEN_ADDR_BIG_ENDIAN |
162 | #define CONFIG_SMP_PEN_ADDR 0x01ee0200 | |
1a2826f6 | 163 | |
c8a7d9da | 164 | #define CONFIG_HWCONFIG |
03c22449 ZZ |
165 | #define HWCONFIG_BUFFER_SIZE 256 |
166 | ||
167 | #define CONFIG_FSL_DEVICE_DISABLE | |
c8a7d9da | 168 | |
a65d7408 AW |
169 | #define BOOT_TARGET_DEVICES(func) \ |
170 | func(MMC, mmc, 0) \ | |
d2c49aad YD |
171 | func(USB, usb, 0) \ |
172 | func(DHCP, dhcp, na) | |
a65d7408 | 173 | #include <config_distro_bootcmd.h> |
c8a7d9da | 174 | |
55d53ab4 AW |
175 | #ifdef CONFIG_LPUART |
176 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
33c3dfd2 AW |
177 | "bootargs=root=/dev/ram0 rw console=ttyLP0,115200 " \ |
178 | "cma=64M@0x0-0xb0000000\0" \ | |
7ff7166c | 179 | "initrd_high=0xffffffff\0" \ |
a65d7408 AW |
180 | "kernel_addr=0x65000000\0" \ |
181 | "scriptaddr=0x80000000\0" \ | |
b8ae6798 | 182 | "scripthdraddr=0x80080000\0" \ |
a65d7408 AW |
183 | "fdtheader_addr_r=0x80100000\0" \ |
184 | "kernelheader_addr_r=0x80200000\0" \ | |
185 | "kernel_addr_r=0x81000000\0" \ | |
186 | "fdt_addr_r=0x90000000\0" \ | |
187 | "ramdisk_addr_r=0xa0000000\0" \ | |
188 | "load_addr=0xa0000000\0" \ | |
189 | "kernel_size=0x2800000\0" \ | |
397a173e SL |
190 | "kernel_addr_sd=0x8000\0" \ |
191 | "kernel_size_sd=0x14000\0" \ | |
feb8fa2e | 192 | "othbootargs=cma=64M@0x0-0xb0000000\0" \ |
a65d7408 AW |
193 | BOOTENV \ |
194 | "boot_scripts=ls1021atwr_boot.scr\0" \ | |
b8ae6798 | 195 | "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \ |
a65d7408 AW |
196 | "scan_dev_for_boot_part=" \ |
197 | "part list ${devtype} ${devnum} devplist; " \ | |
198 | "env exists devplist || setenv devplist 1; " \ | |
199 | "for distro_bootpart in ${devplist}; do " \ | |
200 | "if fstype ${devtype} " \ | |
201 | "${devnum}:${distro_bootpart} " \ | |
202 | "bootfstype; then " \ | |
203 | "run scan_dev_for_boot; " \ | |
204 | "fi; " \ | |
205 | "done\0" \ | |
b8ae6798 SG |
206 | "scan_dev_for_boot=" \ |
207 | "echo Scanning ${devtype} " \ | |
208 | "${devnum}:${distro_bootpart}...; " \ | |
209 | "for prefix in ${boot_prefixes}; do " \ | |
210 | "run scan_dev_for_scripts; " \ | |
211 | "done;" \ | |
212 | "\0" \ | |
213 | "boot_a_script=" \ | |
214 | "load ${devtype} ${devnum}:${distro_bootpart} " \ | |
215 | "${scriptaddr} ${prefix}${script}; " \ | |
216 | "env exists secureboot && load ${devtype} " \ | |
217 | "${devnum}:${distro_bootpart} " \ | |
78c58082 VP |
218 | "${scripthdraddr} ${prefix}${boot_script_hdr}; " \ |
219 | "env exists secureboot " \ | |
b8ae6798 SG |
220 | "&& esbc_validate ${scripthdraddr};" \ |
221 | "source ${scriptaddr}\0" \ | |
a65d7408 AW |
222 | "installer=load mmc 0:2 $load_addr " \ |
223 | "/flex_installer_arm32.itb; " \ | |
224 | "bootm $load_addr#ls1021atwr\0" \ | |
225 | "qspi_bootcmd=echo Trying load from qspi..;" \ | |
226 | "sf probe && sf read $load_addr " \ | |
227 | "$kernel_addr $kernel_size && bootm $load_addr#$board\0" \ | |
228 | "nor_bootcmd=echo Trying load from nor..;" \ | |
229 | "cp.b $kernel_addr $load_addr " \ | |
230 | "$kernel_size && bootm $load_addr#$board\0" | |
55d53ab4 | 231 | #else |
c8a7d9da | 232 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
33c3dfd2 AW |
233 | "bootargs=root=/dev/ram0 rw console=ttyS0,115200 " \ |
234 | "cma=64M@0x0-0xb0000000\0" \ | |
7ff7166c | 235 | "initrd_high=0xffffffff\0" \ |
9b457cc6 VPB |
236 | "kernel_addr=0x61000000\0" \ |
237 | "kernelheader_addr=0x60800000\0" \ | |
a65d7408 | 238 | "scriptaddr=0x80000000\0" \ |
b8ae6798 | 239 | "scripthdraddr=0x80080000\0" \ |
a65d7408 AW |
240 | "fdtheader_addr_r=0x80100000\0" \ |
241 | "kernelheader_addr_r=0x80200000\0" \ | |
242 | "kernel_addr_r=0x81000000\0" \ | |
9b457cc6 | 243 | "kernelheader_size=0x40000\0" \ |
a65d7408 AW |
244 | "fdt_addr_r=0x90000000\0" \ |
245 | "ramdisk_addr_r=0xa0000000\0" \ | |
246 | "load_addr=0xa0000000\0" \ | |
247 | "kernel_size=0x2800000\0" \ | |
9b457cc6 VPB |
248 | "kernel_addr_sd=0x8000\0" \ |
249 | "kernel_size_sd=0x14000\0" \ | |
250 | "kernelhdr_addr_sd=0x4000\0" \ | |
251 | "kernelhdr_size_sd=0x10\0" \ | |
feb8fa2e | 252 | "othbootargs=cma=64M@0x0-0xb0000000\0" \ |
a65d7408 AW |
253 | BOOTENV \ |
254 | "boot_scripts=ls1021atwr_boot.scr\0" \ | |
b8ae6798 | 255 | "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \ |
a65d7408 AW |
256 | "scan_dev_for_boot_part=" \ |
257 | "part list ${devtype} ${devnum} devplist; " \ | |
258 | "env exists devplist || setenv devplist 1; " \ | |
259 | "for distro_bootpart in ${devplist}; do " \ | |
260 | "if fstype ${devtype} " \ | |
261 | "${devnum}:${distro_bootpart} " \ | |
262 | "bootfstype; then " \ | |
263 | "run scan_dev_for_boot; " \ | |
264 | "fi; " \ | |
265 | "done\0" \ | |
b8ae6798 SG |
266 | "scan_dev_for_boot=" \ |
267 | "echo Scanning ${devtype} " \ | |
268 | "${devnum}:${distro_bootpart}...; " \ | |
269 | "for prefix in ${boot_prefixes}; do " \ | |
270 | "run scan_dev_for_scripts; " \ | |
271 | "done;" \ | |
272 | "\0" \ | |
273 | "boot_a_script=" \ | |
274 | "load ${devtype} ${devnum}:${distro_bootpart} " \ | |
275 | "${scriptaddr} ${prefix}${script}; " \ | |
276 | "env exists secureboot && load ${devtype} " \ | |
277 | "${devnum}:${distro_bootpart} " \ | |
278 | "${scripthdraddr} ${prefix}${boot_script_hdr} " \ | |
279 | "&& esbc_validate ${scripthdraddr};" \ | |
280 | "source ${scriptaddr}\0" \ | |
a65d7408 AW |
281 | "qspi_bootcmd=echo Trying load from qspi..;" \ |
282 | "sf probe && sf read $load_addr " \ | |
9b457cc6 VPB |
283 | "$kernel_addr $kernel_size; env exists secureboot " \ |
284 | "&& sf read $kernelheader_addr_r $kernelheader_addr " \ | |
285 | "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ | |
286 | "bootm $load_addr#$board\0" \ | |
a65d7408 AW |
287 | "nor_bootcmd=echo Trying load from nor..;" \ |
288 | "cp.b $kernel_addr $load_addr " \ | |
9b457cc6 VPB |
289 | "$kernel_size; env exists secureboot " \ |
290 | "&& cp.b $kernelheader_addr $kernelheader_addr_r " \ | |
291 | "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ | |
292 | "bootm $load_addr#$board\0" \ | |
397a173e SL |
293 | "sd_bootcmd=echo Trying load from SD ..;" \ |
294 | "mmcinfo && mmc read $load_addr " \ | |
295 | "$kernel_addr_sd $kernel_size_sd && " \ | |
9b457cc6 VPB |
296 | "env exists secureboot && mmc read $kernelheader_addr_r " \ |
297 | "$kernelhdr_addr_sd $kernelhdr_size_sd " \ | |
298 | " && esbc_validate ${kernelheader_addr_r};" \ | |
397a173e | 299 | "bootm $load_addr#$board\0" |
55d53ab4 | 300 | #endif |
c8a7d9da WH |
301 | |
302 | /* | |
303 | * Miscellaneous configurable options | |
304 | */ | |
c463eeb4 | 305 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) |
c8a7d9da | 306 | |
660673af XL |
307 | #define CONFIG_LS102XA_STREAM_ID |
308 | ||
c8a7d9da WH |
309 | /* |
310 | * Environment | |
311 | */ | |
c8a7d9da | 312 | |
ef6c55a2 | 313 | #include <asm/fsl_secure_boot.h> |
4ba4a095 | 314 | |
c8a7d9da | 315 | #endif |