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1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
2 | /* | |
3 | * Copyright 2021 Collabora Ltd. | |
4 | */ | |
5 | ||
6 | #ifndef __IMX8MN_VAR_SOM_H | |
7 | #define __IMX8MN_VAR_SOM_H | |
8 | ||
9 | #include <linux/sizes.h> | |
10 | #include <linux/stringify.h> | |
11 | #include <asm/arch/imx-regs.h> | |
12 | ||
c4c1ed68 AA |
13 | #define CONFIG_SYS_UBOOT_BASE \ |
14 | (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) | |
15 | ||
c4c1ed68 AA |
16 | #define BOOT_TARGET_DEVICES(func) \ |
17 | func(MMC, mmc, 1) \ | |
18 | func(MMC, mmc, 2) \ | |
19 | func(MMC, mmc, 0) \ | |
20 | func(PXE, pxe, na) \ | |
21 | func(DHCP, dhcp, na) \ | |
22 | ||
23 | #include <config_distro_bootcmd.h> | |
24 | ||
c4c1ed68 AA |
25 | #define MEM_LAYOUT_ENV_SETTINGS \ |
26 | "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ | |
27 | "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ | |
28 | "ramdisk_addr_r=0x43800000\0" \ | |
29 | "fdt_addr_r=0x43000000\0" \ | |
30 | "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ | |
31 | "fastboot_partition_alias_all=" \ | |
32 | __stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) ".0:0\0" \ | |
33 | "fastboot_partition_alias_bootloader=" \ | |
34 | __stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) ".1:0\0" \ | |
35 | "emmc_dev=" __stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) "\0" \ | |
36 | "emmc_ack=1\0" \ | |
37 | "pxefile_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ | |
38 | ||
39 | /* Initial environment variables */ | |
40 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
41 | MEM_LAYOUT_ENV_SETTINGS \ | |
42 | BOOTENV | |
43 | ||
44 | /* Link Definitions */ | |
45 | ||
46 | #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 | |
47 | #define CONFIG_SYS_INIT_RAM_SIZE SZ_512K | |
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48 | |
49 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 | |
50 | #define PHYS_SDRAM 0x40000000 | |
51 | #define PHYS_SDRAM_SIZE SZ_1G /* 1GB DDR */ | |
52 | ||
c4c1ed68 AA |
53 | /* USDHC */ |
54 | #define CONFIG_SYS_FSL_ESDHC_ADDR 0 | |
55 | ||
c4c1ed68 | 56 | #endif /* __IMX8MN_VAR_SOM_H */ |