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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
49249e13 PA |
2 | /* |
3 | * Copyright 2010-2011 Freescale Semiconductor, Inc. | |
2703e640 | 4 | * Copyright 2020 NXP |
49249e13 PA |
5 | */ |
6 | ||
7 | /* | |
8 | * P010 RDB board configuration file | |
9 | */ | |
10 | ||
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
1af3c7f4 SG |
14 | #include <linux/stringify.h> |
15 | ||
74fa22ed | 16 | #include <asm/config_mpc85xx.h> |
49249e13 PA |
17 | |
18 | #ifdef CONFIG_SDCARD | |
c9e1f588 YZ |
19 | #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) |
20 | #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) | |
21 | #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) | |
22 | #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) | |
49249e13 PA |
23 | #endif |
24 | ||
25 | #ifdef CONFIG_SPIFLASH | |
bef18454 | 26 | #ifdef CONFIG_NXP_ESBC |
49249e13 | 27 | #define CONFIG_RAMBOOT_SPIFLASH |
84e0fb40 | 28 | #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc |
c9e1f588 | 29 | #else |
c9e1f588 YZ |
30 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) |
31 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) | |
32 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) | |
33 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) | |
c9e1f588 | 34 | #endif |
49249e13 PA |
35 | #endif |
36 | ||
88718be3 | 37 | #ifdef CONFIG_MTD_RAW_NAND |
bef18454 | 38 | #ifdef CONFIG_NXP_ESBC |
e222b1f3 | 39 | #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) |
0fa934d2 PK |
40 | #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) |
41 | #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 | |
c9e1f588 | 42 | #else |
c9e1f588 | 43 | #ifdef CONFIG_TPL_BUILD |
c9e1f588 YZ |
44 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) |
45 | #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) | |
46 | #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) | |
c9e1f588 | 47 | #elif defined(CONFIG_SPL_BUILD) |
c9e1f588 YZ |
48 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) |
49 | #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 | |
50 | #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 | |
c9e1f588 | 51 | #endif |
c9e1f588 | 52 | #endif |
d793e5a8 | 53 | #endif |
2f439e80 RG |
54 | |
55 | #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ | |
e222b1f3 | 56 | #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc |
2f439e80 RG |
57 | #endif |
58 | ||
49249e13 PA |
59 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
60 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
61 | #endif | |
62 | ||
49249e13 | 63 | /* High Level Configuration Options */ |
49249e13 | 64 | |
49249e13 | 65 | #if defined(CONFIG_PCI) |
49249e13 PA |
66 | /* |
67 | * PCI Windows | |
68 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
69 | */ | |
70 | /* controller 1, Slot 1, tgtid 1, Base address a000 */ | |
49249e13 PA |
71 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 |
72 | #ifdef CONFIG_PHYS_64BIT | |
49249e13 PA |
73 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull |
74 | #else | |
49249e13 PA |
75 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 |
76 | #endif | |
49249e13 | 77 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 |
49249e13 PA |
78 | #ifdef CONFIG_PHYS_64BIT |
79 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull | |
80 | #else | |
81 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 | |
82 | #endif | |
83 | ||
84 | /* controller 2, Slot 2, tgtid 2, Base address 9000 */ | |
9de7c76b HZ |
85 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 |
86 | #ifdef CONFIG_PHYS_64BIT | |
87 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull | |
88 | #else | |
89 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 | |
90 | #endif | |
91 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 | |
92 | #ifdef CONFIG_PHYS_64BIT | |
93 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull | |
94 | #else | |
95 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 | |
96 | #endif | |
49249e13 PA |
97 | #endif |
98 | ||
49249e13 PA |
99 | #define CONFIG_HWCONFIG |
100 | /* | |
101 | * These can be toggled for performance analysis, otherwise use default. | |
102 | */ | |
103 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
49249e13 | 104 | |
49249e13 | 105 | /* DDR Setup */ |
49249e13 PA |
106 | #define SPD_EEPROM_ADDRESS 0x52 |
107 | ||
108 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
109 | ||
110 | #ifndef __ASSEMBLY__ | |
111 | extern unsigned long get_sdram_size(void); | |
112 | #endif | |
113 | #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ | |
114 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
115 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
116 | ||
49249e13 PA |
117 | #define CONFIG_SYS_CCSRBAR 0xffe00000 |
118 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
119 | ||
120 | /* | |
121 | * Memory map | |
122 | * | |
123 | * 0x0000_0000 0x3fff_ffff DDR 1G cacheable | |
124 | * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable | |
125 | * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable | |
126 | * | |
127 | * Localbus non-cacheable | |
128 | * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable | |
129 | * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable | |
130 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 | |
131 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable | |
132 | */ | |
133 | ||
49249e13 PA |
134 | /* |
135 | * IFC Definitions | |
136 | */ | |
137 | /* NOR Flash on IFC */ | |
0fa934d2 | 138 | |
49249e13 | 139 | #define CONFIG_SYS_FLASH_BASE 0xee000000 |
49249e13 PA |
140 | |
141 | #ifdef CONFIG_PHYS_64BIT | |
142 | #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) | |
143 | #else | |
144 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
145 | #endif | |
146 | ||
147 | #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
148 | CSPR_PORT_SIZE_16 | \ | |
149 | CSPR_MSEL_NOR | \ | |
150 | CSPR_V) | |
151 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) | |
152 | #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) | |
153 | /* NOR Flash Timing Params */ | |
154 | #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ | |
155 | FTIM0_NOR_TEADC(0x5) | \ | |
156 | FTIM0_NOR_TEAHC(0x5) | |
157 | #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ | |
158 | FTIM1_NOR_TRAD_NOR(0x0f) | |
159 | #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ | |
160 | FTIM2_NOR_TCH(0x4) | \ | |
161 | FTIM2_NOR_TWP(0x1c) | |
162 | #define CONFIG_SYS_NOR_FTIM3 0x0 | |
163 | ||
164 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} | |
49249e13 | 165 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
49249e13 | 166 | |
49249e13 | 167 | /* CFI for NOR Flash */ |
49249e13 PA |
168 | |
169 | /* NAND Flash on IFC */ | |
170 | #define CONFIG_SYS_NAND_BASE 0xff800000 | |
171 | #ifdef CONFIG_PHYS_64BIT | |
172 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull | |
173 | #else | |
174 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
175 | #endif | |
176 | ||
ac688078 | 177 | #define CONFIG_MTD_PARTITION |
ac688078 | 178 | |
49249e13 PA |
179 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
180 | | CSPR_PORT_SIZE_8 \ | |
181 | | CSPR_MSEL_NAND \ | |
182 | | CSPR_V) | |
183 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) | |
e512c50b | 184 | |
7601686c | 185 | #if defined(CONFIG_TARGET_P1010RDB_PA) |
49249e13 PA |
186 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ |
187 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
188 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
189 | | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ | |
190 | | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ | |
191 | | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ | |
192 | | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ | |
e512c50b | 193 | |
7601686c | 194 | #elif defined(CONFIG_TARGET_P1010RDB_PB) |
e512c50b SL |
195 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ |
196 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
197 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
198 | | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ | |
199 | | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ | |
200 | | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ | |
201 | | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ | |
e512c50b | 202 | #endif |
49249e13 | 203 | |
d793e5a8 | 204 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } |
d793e5a8 | 205 | |
7601686c | 206 | #if defined(CONFIG_TARGET_P1010RDB_PA) |
49249e13 PA |
207 | /* NAND Flash Timing Params */ |
208 | #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ | |
209 | FTIM0_NAND_TWP(0x0C) | \ | |
210 | FTIM0_NAND_TWCHT(0x04) | \ | |
211 | FTIM0_NAND_TWH(0x05) | |
212 | #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ | |
213 | FTIM1_NAND_TWBE(0x1d) | \ | |
214 | FTIM1_NAND_TRR(0x07) | \ | |
215 | FTIM1_NAND_TRP(0x0c) | |
216 | #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ | |
217 | FTIM2_NAND_TREH(0x05) | \ | |
218 | FTIM2_NAND_TWHRE(0x0f) | |
219 | #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) | |
220 | ||
7601686c | 221 | #elif defined(CONFIG_TARGET_P1010RDB_PB) |
e512c50b SL |
222 | /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ |
223 | /* ONFI NAND Flash mode0 Timing Params */ | |
224 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ | |
225 | FTIM0_NAND_TWP(0x18) | \ | |
226 | FTIM0_NAND_TWCHT(0x07) | \ | |
227 | FTIM0_NAND_TWH(0x0a)) | |
228 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ | |
229 | FTIM1_NAND_TWBE(0x39) | \ | |
230 | FTIM1_NAND_TRR(0x0e) | \ | |
231 | FTIM1_NAND_TRP(0x18)) | |
232 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ | |
233 | FTIM2_NAND_TREH(0x0a) | \ | |
234 | FTIM2_NAND_TWHRE(0x1e)) | |
235 | #define CONFIG_SYS_NAND_FTIM3 0x0 | |
236 | #endif | |
237 | ||
49249e13 PA |
238 | #define CONFIG_SYS_NAND_DDR_LAW 11 |
239 | ||
240 | /* Set up IFC registers for boot location NOR/NAND */ | |
88718be3 | 241 | #if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT) |
d793e5a8 DD |
242 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR |
243 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
244 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
245 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
246 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
247 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
248 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
249 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR | |
250 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
251 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
252 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
253 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
254 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
255 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
256 | #else | |
49249e13 PA |
257 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR |
258 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
259 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
260 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
261 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
262 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
263 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
264 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR | |
265 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK | |
266 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR | |
267 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
268 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
269 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
270 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
d793e5a8 DD |
271 | #endif |
272 | ||
49249e13 PA |
273 | /* CPLD on IFC */ |
274 | #define CONFIG_SYS_CPLD_BASE 0xffb00000 | |
275 | ||
276 | #ifdef CONFIG_PHYS_64BIT | |
277 | #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull | |
278 | #else | |
279 | #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE | |
280 | #endif | |
281 | ||
282 | #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ | |
283 | | CSPR_PORT_SIZE_8 \ | |
284 | | CSPR_MSEL_GPCM \ | |
285 | | CSPR_V) | |
286 | #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) | |
287 | #define CONFIG_SYS_CSOR3 0x0 | |
288 | /* CPLD Timing parameters for IFC CS3 */ | |
289 | #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ | |
290 | FTIM0_GPCM_TEADC(0x0e) | \ | |
291 | FTIM0_GPCM_TEAHC(0x0e)) | |
292 | #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ | |
293 | FTIM1_GPCM_TRAD(0x1f)) | |
294 | #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ | |
de519163 | 295 | FTIM2_GPCM_TCH(0x8) | \ |
49249e13 PA |
296 | FTIM2_GPCM_TWP(0x1f)) |
297 | #define CONFIG_SYS_CS3_FTIM3 0x0 | |
49249e13 | 298 | |
49249e13 | 299 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ |
b39d1213 | 300 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ |
49249e13 | 301 | |
4c97c8cd | 302 | #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
49249e13 | 303 | |
c9e1f588 YZ |
304 | /* |
305 | * Config the L2 Cache as L2 SRAM | |
306 | */ | |
307 | #if defined(CONFIG_SPL_BUILD) | |
308 | #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) | |
309 | #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 | |
310 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
c9e1f588 | 311 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) |
88718be3 | 312 | #elif defined(CONFIG_MTD_RAW_NAND) |
c9e1f588 YZ |
313 | #ifdef CONFIG_TPL_BUILD |
314 | #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 | |
315 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
c9e1f588 | 316 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) |
c9e1f588 YZ |
317 | #else |
318 | #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 | |
319 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
c9e1f588 | 320 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) |
c9e1f588 YZ |
321 | #endif |
322 | #endif | |
323 | #endif | |
324 | ||
49249e13 | 325 | /* Serial Port */ |
49249e13 | 326 | #undef CONFIG_SERIAL_SOFTWARE_FIFO |
49249e13 PA |
327 | #define CONFIG_SYS_NS16550_SERIAL |
328 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
329 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
b35316fb | 330 | #if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(INIT_MINIMAL) |
d793e5a8 DD |
331 | #define CONFIG_NS16550_MIN_FUNCTIONS |
332 | #endif | |
49249e13 | 333 | |
49249e13 PA |
334 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
335 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
336 | ||
337 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
338 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
339 | ||
00f792e0 | 340 | /* I2C */ |
ad89da0c | 341 | #define I2C_PCA9557_ADDR1 0x18 |
e512c50b | 342 | #define I2C_PCA9557_ADDR2 0x19 |
ad89da0c | 343 | #define I2C_PCA9557_BUS_NUM 0 |
49249e13 PA |
344 | |
345 | /* I2C EEPROM */ | |
7601686c | 346 | #if defined(CONFIG_TARGET_P1010RDB_PB) |
e512c50b SL |
347 | #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ |
348 | #endif | |
49249e13 | 349 | /* enable read and write access to EEPROM */ |
49249e13 PA |
350 | |
351 | /* RTC */ | |
352 | #define CONFIG_RTC_PT7C4338 | |
353 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
354 | ||
49249e13 PA |
355 | /* |
356 | * SPI interface will not be available in case of NAND boot SPI CS0 will be | |
357 | * used for SLIC | |
358 | */ | |
88718be3 | 359 | #if !defined(CONFIG_MTD_RAW_NAND) || !defined(CONFIG_NAND_SECBOOT) |
49249e13 | 360 | /* eSPI - Enhanced SPI */ |
d793e5a8 | 361 | #endif |
49249e13 PA |
362 | |
363 | #if defined(CONFIG_TSEC_ENET) | |
49249e13 PA |
364 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ |
365 | #define CONFIG_TSEC1 1 | |
366 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
367 | #define CONFIG_TSEC2 1 | |
368 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
369 | #define CONFIG_TSEC3 1 | |
370 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
371 | ||
372 | #define TSEC1_PHY_ADDR 1 | |
373 | #define TSEC2_PHY_ADDR 0 | |
374 | #define TSEC3_PHY_ADDR 2 | |
375 | ||
376 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
377 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
378 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
379 | ||
380 | #define TSEC1_PHYIDX 0 | |
381 | #define TSEC2_PHYIDX 0 | |
382 | #define TSEC3_PHYIDX 0 | |
383 | ||
49249e13 PA |
384 | /* TBI PHY configuration for SGMII mode */ |
385 | #define CONFIG_TSEC_TBICR_SETTINGS ( \ | |
386 | TBICR_PHY_RESET \ | |
387 | | TBICR_ANEG_ENABLE \ | |
388 | | TBICR_FULL_DUPLEX \ | |
389 | | TBICR_SPEED1_SET \ | |
390 | ) | |
391 | ||
392 | #endif /* CONFIG_TSEC_ENET */ | |
393 | ||
49249e13 | 394 | #ifdef CONFIG_MMC |
49249e13 PA |
395 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR |
396 | #endif | |
397 | ||
49249e13 PA |
398 | /* |
399 | * Environment | |
400 | */ | |
d8e84617 | 401 | #if defined(CONFIG_MTD_RAW_NAND) |
c9e1f588 | 402 | #ifdef CONFIG_TPL_BUILD |
a09fea1d | 403 | #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) |
c9e1f588 | 404 | #endif |
49249e13 PA |
405 | #endif |
406 | ||
8850c5d5 | 407 | #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \ |
49249e13 | 408 | || defined(CONFIG_FSL_SATA) |
49249e13 PA |
409 | #endif |
410 | ||
411 | /* | |
412 | * Miscellaneous configurable options | |
413 | */ | |
49249e13 | 414 | |
49249e13 PA |
415 | /* |
416 | * For booting Linux, the board info and command line data | |
417 | * have to be in the first 64 MB of memory, since this is | |
418 | * the maximum mapped by the Linux kernel during initialization. | |
419 | */ | |
420 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ | |
49249e13 | 421 | |
49249e13 PA |
422 | /* |
423 | * Environment Configuration | |
424 | */ | |
425 | ||
8b3637c6 | 426 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
49249e13 PA |
427 | #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ |
428 | ||
49249e13 | 429 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
5368c55d | 430 | "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ |
49249e13 | 431 | "netdev=eth0\0" \ |
5368c55d | 432 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
49249e13 PA |
433 | "loadaddr=1000000\0" \ |
434 | "consoledev=ttyS0\0" \ | |
435 | "ramdiskaddr=2000000\0" \ | |
436 | "ramdiskfile=rootfs.ext2.gz.uboot\0" \ | |
b24a4f62 | 437 | "fdtaddr=1e00000\0" \ |
49249e13 PA |
438 | "fdtfile=p1010rdb.dtb\0" \ |
439 | "bdev=sda1\0" \ | |
440 | "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ | |
441 | "othbootargs=ramdisk_size=600000\0" \ | |
442 | "usbfatboot=setenv bootargs root=/dev/ram rw " \ | |
443 | "console=$consoledev,$baudrate $othbootargs; " \ | |
444 | "usb start;" \ | |
445 | "fatload usb 0:2 $loadaddr $bootfile;" \ | |
446 | "fatload usb 0:2 $fdtaddr $fdtfile;" \ | |
447 | "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ | |
448 | "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ | |
449 | "usbext2boot=setenv bootargs root=/dev/ram rw " \ | |
450 | "console=$consoledev,$baudrate $othbootargs; " \ | |
451 | "usb start;" \ | |
452 | "ext2load usb 0:4 $loadaddr $bootfile;" \ | |
453 | "ext2load usb 0:4 $fdtaddr $fdtfile;" \ | |
454 | "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ | |
e512c50b | 455 | "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ |
028aa094 | 456 | BOOTMODE |
e512c50b | 457 | |
7601686c | 458 | #if defined(CONFIG_TARGET_P1010RDB_PA) |
028aa094 | 459 | #define BOOTMODE \ |
e512c50b SL |
460 | "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ |
461 | "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ | |
462 | "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ | |
463 | "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \ | |
464 | "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ | |
465 | "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" | |
466 | ||
7601686c | 467 | #elif defined(CONFIG_TARGET_P1010RDB_PB) |
028aa094 | 468 | #define BOOTMODE \ |
e512c50b SL |
469 | "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ |
470 | "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ | |
471 | "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ | |
472 | "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \ | |
473 | "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \ | |
474 | "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \ | |
475 | "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \ | |
476 | "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \ | |
477 | "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \ | |
478 | "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" | |
479 | #endif | |
49249e13 | 480 | |
2f439e80 | 481 | #include <asm/fsl_secure_boot.h> |
2f439e80 | 482 | |
49249e13 | 483 | #endif /* __CONFIG_H */ |