[J-u-boot.git] / board / sandburst / karef / karef.c

/*
 *  Copyright (C) 2005 Sandburst Corporation
 *  Travis B. Sawyer
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <common.h>
#include <command.h>
#include "karef.h"
#include "karef_version.h"
#include <asm/processor.h>
#include <asm/io.h>
#include <spd_sdram.h>
#include <i2c.h>
#include "../common/sb_common.h"
#include "../common/ppc440gx_i2c.h"

void fpga_init (void);

KAREF_BOARD_ID_ST board_id_as[] =
{
	{"Undefined"},			     /* Not specified */
	{"Kamino Reference Design"},
	{"Reserved"},			     /* Reserved for future use */
	{"Reserved"},			     /* Reserved for future use */
};

KAREF_BOARD_ID_ST ofem_board_id_as[] =
{
	{"Undefined"},
	{"1x10 + 10x2"},
	{"Reserved"},
	{"Reserved"},
};

/*************************************************************************
 *  board_early_init_f
 *
 *  Setup chip selects, initialize the Opto-FPGA, initialize
 *  interrupt polarity and triggers.
 ************************************************************************/
int board_early_init_f (void)
{
	ppc440_gpio_regs_t *gpio_regs;

	/* Enable GPIO interrupts */
	mtsdr(sdr_pfc0, 0x00103E00);

	/* Setup access for LEDs, and system topology info */
	gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE;
	gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
	gpio_regs->tri_state  = SBCOMMON_GPIO_DBGLEDS;

	/* Turn on all the leds for now */
	gpio_regs->out = SBCOMMON_GPIO_LEDS;

	/*--------------------------------------------------------------------+
	  | Initialize EBC CONFIG
	  +-------------------------------------------------------------------*/
	mtebc(xbcfg,
	      EBC_CFG_LE_UNLOCK	   | EBC_CFG_PTD_ENABLE |
	      EBC_CFG_RTC_64PERCLK | EBC_CFG_ATC_PREVIOUS |
	      EBC_CFG_DTC_PREVIOUS | EBC_CFG_CTC_PREVIOUS |
	      EBC_CFG_EMC_DEFAULT  | EBC_CFG_PME_DISABLE |
	      EBC_CFG_PR_32);

	/*--------------------------------------------------------------------+
	  | 1/2 MB FLASH. Initialize bank 0 with default values.
	  +-------------------------------------------------------------------*/
	mtebc(pb0ap,
	      EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
	      EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
	      EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
	      EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
	      EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
	      EBC_BXAP_PEN_DISABLED);

	mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) |
	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
	/*--------------------------------------------------------------------+
	  | 8KB NVRAM/RTC. Initialize bank 1 with default values.
	  +-------------------------------------------------------------------*/
	mtebc(pb1ap,
	      EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(10) |
	      EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
	      EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
	      EBC_BXAP_WBF_ENCODE(1)| EBC_BXAP_TH_ENCODE(1) |
	      EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
	      EBC_BXAP_PEN_DISABLED);

	mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000) |
	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);

	/*--------------------------------------------------------------------+
	  | Compact Flash, uses 2 Chip Selects (2 & 6)
	  +-------------------------------------------------------------------*/
	mtebc(pb2ap,
	      EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
	      EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
	      EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
	      EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
	      EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
	      EBC_BXAP_PEN_DISABLED);

	mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xF0000000) |
	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);

	/*--------------------------------------------------------------------+
	  | KaRef Scan FPGA. Initialize bank 3 with default values.
	  +-------------------------------------------------------------------*/
	mtebc(pb5ap,
	      EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
	      EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
	      EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
	      EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);

	mtebc(pb5cr, EBC_BXCR_BAS_ENCODE(0x48200000) |
	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);

	/*--------------------------------------------------------------------+
	  | MAC A & B for Kamino.  OFEM FPGA decodes the addresses
	  | Initialize bank 4 with default values.
	  +-------------------------------------------------------------------*/
	mtebc(pb4ap,
	      EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
	      EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
	      EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
	      EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);

	mtebc(pb4cr, EBC_BXCR_BAS_ENCODE(0x48600000) |
	      EBC_BXCR_BS_2MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);

	/*--------------------------------------------------------------------+
	  | OFEM FPGA  Initialize bank 5 with default values.
	  +-------------------------------------------------------------------*/
	mtebc(pb3ap,
	      EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
	      EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
	      EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
	      EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);


	mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48400000) |
	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);


	/*--------------------------------------------------------------------+
	  | Compact Flash, uses 2 Chip Selects (2 & 6)
	  +-------------------------------------------------------------------*/
	mtebc(pb6ap,
	      EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(8) |
	      EBC_BXAP_BCE_DISABLE  | EBC_BXAP_CSN_ENCODE(1) |
	      EBC_BXAP_OEN_ENCODE(1)| EBC_BXAP_WBN_ENCODE(1) |
	      EBC_BXAP_WBF_ENCODE(0)| EBC_BXAP_TH_ENCODE(1) |
	      EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
	      EBC_BXAP_PEN_DISABLED);

	mtebc(pb6cr, EBC_BXCR_BAS_ENCODE(0xF0100000) |
	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);

	/*--------------------------------------------------------------------+
	  | BME-32. Initialize bank 7 with default values.
	  +-------------------------------------------------------------------*/
	mtebc(pb7ap,
	      EBC_BXAP_RE_ENABLED    | EBC_BXAP_SOR_NONDELAYED |
	      EBC_BXAP_BME_DISABLED  | EBC_BXAP_TWT_ENCODE(3) |
	      EBC_BXAP_TH_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(0) |
	      EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_PEN_DISABLED |
	      EBC_BXAP_OEN_ENCODE(1) | EBC_BXAP_BEM_RW);

	mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) |
	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);

	/*--------------------------------------------------------------------+
	 * Setup the interrupt controller polarities, triggers, etc.
	 +-------------------------------------------------------------------*/
	mtdcr (uic0sr, 0xffffffff);	/* clear all */
	mtdcr (uic0er, 0x00000000);	/* disable all */
	mtdcr (uic0cr, 0x00000000);	/* all non- critical */
	mtdcr (uic0pr, 0xfffffe03);	/* polarity */
	mtdcr (uic0tr, 0x01c00000);	/* trigger edge vs level */
	mtdcr (uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr (uic0sr, 0xffffffff);	/* clear all */

	mtdcr (uic1sr, 0xffffffff);	/* clear all */
	mtdcr (uic1er, 0x00000000);	/* disable all */
	mtdcr (uic1cr, 0x00000000);	/* all non-critical */
	mtdcr (uic1pr, 0xffffc8ff);	/* polarity */
	mtdcr (uic1tr, 0x00ff0000);	/* trigger edge vs level */
	mtdcr (uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr (uic1sr, 0xffffffff);	/* clear all */

	mtdcr (uic2sr, 0xffffffff);	/* clear all */
	mtdcr (uic2er, 0x00000000);	/* disable all */
	mtdcr (uic2cr, 0x00000000);	/* all non-critical */
	mtdcr (uic2pr, 0xffff83ff);	/* polarity */
	mtdcr (uic2tr, 0x00ff8c0f);	/* trigger edge vs level */
	mtdcr (uic2vr, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr (uic2sr, 0xffffffff);	/* clear all */

	mtdcr (uicb0sr, 0xfc000000);	/* clear all */
	mtdcr (uicb0er, 0x00000000);	/* disable all */
	mtdcr (uicb0cr, 0x00000000);	/* all non-critical */
	mtdcr (uicb0pr, 0xfc000000);
	mtdcr (uicb0tr, 0x00000000);
	mtdcr (uicb0vr, 0x00000001);

	fpga_init();

	return 0;
}


/*************************************************************************
 *  checkboard
 *
 *  Dump pertinent info to the console
 ************************************************************************/
int checkboard (void)
{
	sys_info_t sysinfo;
	unsigned char brd_rev, brd_id;
	unsigned short sernum;
	unsigned char scan_rev, scan_id, ofem_rev=0, ofem_id=0;
	unsigned char ofem_brd_rev, ofem_brd_id;
	KAREF_FPGA_REGS_ST *karef_ps;
	OFEM_FPGA_REGS_ST *ofem_ps;

	karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
	ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE;

	scan_id = (unsigned char)((karef_ps->revision_ul &
				   SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK)
				  >> SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT);

	scan_rev = (unsigned char)((karef_ps->revision_ul & SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK)
				   >> SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT);

	brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK)
				  >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT);

	brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK)
				 >> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT);

	ofem_brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK)
				      >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT);

	ofem_brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK)
				       >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT);

	if (0xF != ofem_brd_id) {
		ofem_id = (unsigned char)((ofem_ps->revision_ul &
					   SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK)
					  >> SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT);

		ofem_rev = (unsigned char)((ofem_ps->revision_ul &
					    SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK)
					   >> SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT);
	}

	get_sys_info (&sysinfo);

	sernum = sbcommon_get_serial_number();

	printf ("Board: Sandburst Corporation Kamino Reference Design "
		"Serial Number: %d\n", sernum);
	printf ("%s\n", KAREF_U_BOOT_REL_STR);

	printf ("Built %s %s by %s\n", __DATE__, __TIME__, BUILDUSER);
	if (sbcommon_get_master()) {
		printf("Slot 0 - Master\nSlave board");
		if (sbcommon_secondary_present())
			printf(" present\n");
		else
			printf(" not detected\n");
	} else {
		printf("Slot 1 - Slave\n\n");
	}

	printf ("ScanFPGA ID:\t0x%02X\tRev:  0x%02X\n", scan_id, scan_rev);
	printf ("Board Rev:\t0x%02X\tID:   0x%02X\n", brd_rev, brd_id);
	if(0xF != ofem_brd_id) {
		printf("OFemFPGA ID:\t0x%02X\tRev:  0x%02X\n", ofem_id, ofem_rev);
		printf("OFEM Board Rev:\t0x%02X\tID:   0x%02X\n", ofem_brd_id, ofem_brd_rev);
	}

	/* Fix the ack in the bme 32 */
	udelay(5000);
	out32(CFG_BME32_BASE + 0x0000000C, 0x00000001);
	asm("eieio");


	return (0);
}

/*************************************************************************
 *  misc_init_f
 *
 *  Initialize I2C bus one to gain access to the fans
 ************************************************************************/
int misc_init_f (void)
{
	/* Turn on i2c bus 1 */
	puts ("I2C1:  ");
	i2c1_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
	puts ("ready\n");

	/* Turn on fans 3 & 4 */
	sbcommon_fans();

	return (0);
}

/*************************************************************************
 *  misc_init_r
 *
 *  Do nothing.
 ************************************************************************/
int misc_init_r (void)
{
	unsigned short sernum;
	char envstr[255];
	KAREF_FPGA_REGS_ST *karef_ps;
	OFEM_FPGA_REGS_ST *ofem_ps;

	if(NULL != getenv("secondserial")) {
		puts("secondserial is set, switching to second serial port\n");
		setenv("stderr", "serial1");
		setenv("stdout", "serial1");
		setenv("stdin", "serial1");
	}

	setenv("ubrelver", KAREF_U_BOOT_REL_STR);

	memset(envstr, 0, 255);
	sprintf (envstr, "Built %s %s by %s", __DATE__, __TIME__, BUILDUSER);
	setenv("bldstr", envstr);
	saveenv();

	if( getenv("autorecover")) {
		setenv("autorecover", NULL);
		saveenv();
		sernum = sbcommon_get_serial_number();

		printf("\nSetting up environment for automatic filesystem recovery\n");
		/*
		 * Setup default bootargs
		 */
		memset(envstr, 0, 255);

		sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
			"rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33",
			sernum, sernum);
		setenv("bootargs", envstr);

		/*
		 * Setup Default boot command
		 */
		setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;"
		       "fatload ide 0 8100000 pramdisk;"
		       "bootm 8000000 8100000");

		printf("Done.  Please type allow the system to continue to boot\n");
	}

	if( getenv("fakeled")) {
		karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
		ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE;
		ofem_ps->control_ul &= ~SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK;
		karef_ps->control_ul &= ~SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK;
		setenv("bootdelay", "-1");
		saveenv();
		printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
	}

	return (0);
}

/*************************************************************************
 *  ide_set_reset
 ************************************************************************/
#ifdef CONFIG_IDE_RESET
void ide_set_reset(int on)
{
	KAREF_FPGA_REGS_ST *karef_ps;
	/* TODO: ide reset */
	karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;

	if (on) {
		karef_ps->reset_ul &= ~SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
	} else {
		karef_ps->reset_ul |= SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
	}
}
#endif /* CONFIG_IDE_RESET */

/*************************************************************************
 *  fpga_init
 ************************************************************************/
void fpga_init(void)
{
	KAREF_FPGA_REGS_ST *karef_ps;
	OFEM_FPGA_REGS_ST *ofem_ps;
	unsigned char ofem_id;
	unsigned long tmp;

	/* Ensure we have power all around */
	udelay(500);

	karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
	tmp =
		SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK |
		SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK |
		SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK |
		SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK |
		SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK |
		SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK |
		SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK |
		SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK |
		SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK;

	karef_ps->reset_ul = tmp;

	/*
	 * Wait a bit to allow the ofem fpga to get its brains
	 */
	udelay(5000);

	/*
	 * Check to see if the ofem is there
	 */
	ofem_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK)
				  >> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT);
	if(0xF != ofem_id) {
		tmp =
			SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK |
			SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK |
			SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK;

		ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE;
		ofem_ps->reset_ul = tmp;

		ofem_ps->control_ul |= 1 < SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT;
	}

	karef_ps->control_ul |= 1 << SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT;

	asm("eieio");

	return;
}

int karefSetupVars(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	unsigned short sernum;
	char envstr[255];

	sernum = sbcommon_get_serial_number();

	memset(envstr, 0, 255);
	/*
	 * Setup our ip address
	 */
	sprintf(envstr, "10.100.70.%d", sernum);

	setenv("ipaddr", envstr);
	/*
	 * Setup the host ip address
	 */
	setenv("serverip", "10.100.17.10");

	/*
	 * Setup default bootargs
	 */
	memset(envstr, 0, 255);

	sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs "
		"rw nfsroot=10.100.17.10:/home/metrobox/mbc70.%d "
		"nfsaddrs=10.100.70.%d:10.100.17.10:10.100.1.1:"
		"255.255.0.0:karef%d.sandburst.com:eth0:none idebus=33",
		sernum, sernum, sernum);

	setenv("bootargs_nfs", envstr);
	setenv("bootargs", envstr);

	/*
	 * Setup CF bootargs
	 */
	memset(envstr, 0, 255);

	sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 "
		"rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33",
		sernum, sernum);

	setenv("bootargs_cf", envstr);

	/*
	 * Setup Default boot command
	 */
	setenv("bootcmd_tftp", "tftp 8000000 uImage.karef;bootm 8000000");
	setenv("bootcmd", "tftp 8000000 uImage.karef;bootm 8000000");

	/*
	 * Setup compact flash boot command
	 */
	setenv("bootcmd_cf", "fatload ide 0 8000000 uimage.karef;bootm 8000000");

	saveenv();

	return(1);
}

int karefRecover(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
	unsigned short sernum;
	char envstr[255];

	sernum = sbcommon_get_serial_number();

	printf("\nSetting up environment for filesystem recovery\n");
	/*
	 * Setup default bootargs
	 */
	memset(envstr, 0, 255);

	sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
		"rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none",
		sernum, sernum);
	setenv("bootargs", envstr);

	/*
	 * Setup Default boot command
	 */

	setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;"
	       "fatload ide 0 8100000 pramdisk;"
	       "bootm 8000000 8100000");

	printf("Done.  Please type boot<cr>.\nWhen the kernel has booted"
	       " please type fsrecover.sh<cr>\n");

	return(1);
}

U_BOOT_CMD(kasetup, 1, 1, karefSetupVars,
	   "kasetup - Set environment to factory defaults\n", NULL);

U_BOOT_CMD(karecover, 1, 1, karefRecover,
	   "karecover - Set environment to allow for fs recovery\n", NULL);
Commit	Line	Data
b79316f2 SR	1	/*
	2	* Copyright (C) 2005 Sandburst Corporation
	3	* Travis B. Sawyer
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#include <config.h>
	25	#include <common.h>
	26	#include <command.h>
	27	#include "karef.h"
	28	#include "karef_version.h"
	29	#include <asm/processor.h>
	30	#include <asm/io.h>
	31	#include <spd_sdram.h>
	32	#include <i2c.h>
	33	#include "../common/sb_common.h"
	34	#include "../common/ppc440gx_i2c.h"
	35
b79316f2 SR	36	void fpga_init (void);
	37
	38	KAREF_BOARD_ID_ST board_id_as[] =
	39	{
	40	{"Undefined"}, /* Not specified */
	41	{"Kamino Reference Design"},
	42	{"Reserved"}, /* Reserved for future use */
	43	{"Reserved"}, /* Reserved for future use */
	44	};
	45
	46	KAREF_BOARD_ID_ST ofem_board_id_as[] =
	47	{
	48	{"Undefined"},
	49	{"1x10 + 10x2"},
	50	{"Reserved"},
	51	{"Reserved"},
	52	};
	53
b79316f2 SR	54	/*************************************************************************
	55	* board_early_init_f
	56	*
	57	* Setup chip selects, initialize the Opto-FPGA, initialize
	58	* interrupt polarity and triggers.
b79316f2 SR	59	************************************************************************/
	60	int board_early_init_f (void)
	61	{
	62	ppc440_gpio_regs_t *gpio_regs;
	63
	64	/* Enable GPIO interrupts */
	65	mtsdr(sdr_pfc0, 0x00103E00);
	66
	67	/* Setup access for LEDs, and system topology info */
	68	gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE;
	69	gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
	70	gpio_regs->tri_state = SBCOMMON_GPIO_DBGLEDS;
	71
	72	/* Turn on all the leds for now */
	73	gpio_regs->out = SBCOMMON_GPIO_LEDS;
	74
	75	/*--------------------------------------------------------------------+
	76	\| Initialize EBC CONFIG
	77	+-------------------------------------------------------------------*/
	78	mtebc(xbcfg,
	79	EBC_CFG_LE_UNLOCK \| EBC_CFG_PTD_ENABLE \|
	80	EBC_CFG_RTC_64PERCLK \| EBC_CFG_ATC_PREVIOUS \|
	81	EBC_CFG_DTC_PREVIOUS \| EBC_CFG_CTC_PREVIOUS \|
	82	EBC_CFG_EMC_DEFAULT \| EBC_CFG_PME_DISABLE \|
	83	EBC_CFG_PR_32);
	84
	85	/*--------------------------------------------------------------------+
	86	\| 1/2 MB FLASH. Initialize bank 0 with default values.
	87	+-------------------------------------------------------------------*/
	88	mtebc(pb0ap,
	89	EBC_BXAP_BME_DISABLED \| EBC_BXAP_TWT_ENCODE(8) \|
	90	EBC_BXAP_BCE_DISABLE \| EBC_BXAP_CSN_ENCODE(1) \|
	91	EBC_BXAP_OEN_ENCODE(1)\| EBC_BXAP_WBN_ENCODE(1) \|
	92	EBC_BXAP_WBF_ENCODE(1)\| EBC_BXAP_TH_ENCODE(1) \|
	93	EBC_BXAP_RE_DISABLED \| EBC_BXAP_BEM_WRITEONLY \|
	94	EBC_BXAP_PEN_DISABLED);
	95
	96	mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) \|
	97	EBC_BXCR_BS_1MB \| EBC_BXCR_BU_RW \| EBC_BXCR_BW_8BIT);
	98	/*--------------------------------------------------------------------+
	99	\| 8KB NVRAM/RTC. Initialize bank 1 with default values.
	100	+-------------------------------------------------------------------*/
	101	mtebc(pb1ap,
	102	EBC_BXAP_BME_DISABLED \| EBC_BXAP_TWT_ENCODE(10) \|
	103	EBC_BXAP_BCE_DISABLE \| EBC_BXAP_CSN_ENCODE(1) \|
	104	EBC_BXAP_OEN_ENCODE(1)\| EBC_BXAP_WBN_ENCODE(1) \|
	105	EBC_BXAP_WBF_ENCODE(1)\| EBC_BXAP_TH_ENCODE(1) \|
	106	EBC_BXAP_RE_DISABLED \| EBC_BXAP_BEM_WRITEONLY \|
	107	EBC_BXAP_PEN_DISABLED);
	108
	109	mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000) \|
	110	EBC_BXCR_BS_1MB \| EBC_BXCR_BU_RW \| EBC_BXCR_BW_8BIT);
	111
	112	/*--------------------------------------------------------------------+
	113	\| Compact Flash, uses 2 Chip Selects (2 & 6)
	114	+-------------------------------------------------------------------*/
	115	mtebc(pb2ap,
	116	EBC_BXAP_BME_DISABLED \| EBC_BXAP_TWT_ENCODE(8) \|
	117	EBC_BXAP_BCE_DISABLE \| EBC_BXAP_CSN_ENCODE(1) \|
	118	EBC_BXAP_OEN_ENCODE(1)\| EBC_BXAP_WBN_ENCODE(1) \|
	119	EBC_BXAP_WBF_ENCODE(0)\| EBC_BXAP_TH_ENCODE(1) \|
	120	EBC_BXAP_RE_DISABLED \| EBC_BXAP_BEM_WRITEONLY \|
	121	EBC_BXAP_PEN_DISABLED);
	122
123	mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xF0000000) \|
124	EBC_BXCR_BS_1MB \| EBC_BXCR_BU_RW \| EBC_BXCR_BW_16BIT);
125
126	/*--------------------------------------------------------------------+
127	\| KaRef Scan FPGA. Initialize bank 3 with default values.
128	+-------------------------------------------------------------------*/
129	mtebc(pb5ap,
130	EBC_BXAP_RE_ENABLED \| EBC_BXAP_SOR_NONDELAYED \|
131	EBC_BXAP_BME_DISABLED \| EBC_BXAP_TWT_ENCODE(3) \|
132	EBC_BXAP_TH_ENCODE(1) \| EBC_BXAP_WBF_ENCODE(0) \|
133	EBC_BXAP_CSN_ENCODE(1) \| EBC_BXAP_PEN_DISABLED \|
134	EBC_BXAP_OEN_ENCODE(1) \| EBC_BXAP_BEM_RW);
135
136	mtebc(pb5cr, EBC_BXCR_BAS_ENCODE(0x48200000) \|
137	EBC_BXCR_BS_1MB \| EBC_BXCR_BU_RW \| EBC_BXCR_BW_32BIT);
138
139	/*--------------------------------------------------------------------+
140	\| MAC A & B for Kamino. OFEM FPGA decodes the addresses
141	\| Initialize bank 4 with default values.
142	+-------------------------------------------------------------------*/
143	mtebc(pb4ap,
144	EBC_BXAP_RE_ENABLED \| EBC_BXAP_SOR_NONDELAYED \|
145	EBC_BXAP_BME_DISABLED \| EBC_BXAP_TWT_ENCODE(3) \|
146	EBC_BXAP_TH_ENCODE(1) \| EBC_BXAP_WBF_ENCODE(0) \|
147	EBC_BXAP_CSN_ENCODE(1) \| EBC_BXAP_PEN_DISABLED \|
148	EBC_BXAP_OEN_ENCODE(1) \| EBC_BXAP_BEM_RW);
149
150	mtebc(pb4cr, EBC_BXCR_BAS_ENCODE(0x48600000) \|
151	EBC_BXCR_BS_2MB \| EBC_BXCR_BU_RW \| EBC_BXCR_BW_32BIT);
152
153	/*--------------------------------------------------------------------+
154	\| OFEM FPGA Initialize bank 5 with default values.
155	+-------------------------------------------------------------------*/
156	mtebc(pb3ap,
157	EBC_BXAP_RE_ENABLED \| EBC_BXAP_SOR_NONDELAYED \|
158	EBC_BXAP_BME_DISABLED \| EBC_BXAP_TWT_ENCODE(3) \|
159	EBC_BXAP_TH_ENCODE(1) \| EBC_BXAP_WBF_ENCODE(0) \|
160	EBC_BXAP_CSN_ENCODE(1) \| EBC_BXAP_PEN_DISABLED \|
161	EBC_BXAP_OEN_ENCODE(1) \| EBC_BXAP_BEM_RW);
162
163
164	mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48400000) \|
165	EBC_BXCR_BS_1MB \| EBC_BXCR_BU_RW \| EBC_BXCR_BW_32BIT);
166
167
168	/*--------------------------------------------------------------------+
169	\| Compact Flash, uses 2 Chip Selects (2 & 6)
170	+-------------------------------------------------------------------*/
171	mtebc(pb6ap,
172	EBC_BXAP_BME_DISABLED \| EBC_BXAP_TWT_ENCODE(8) \|
173	EBC_BXAP_BCE_DISABLE \| EBC_BXAP_CSN_ENCODE(1) \|
174	EBC_BXAP_OEN_ENCODE(1)\| EBC_BXAP_WBN_ENCODE(1) \|
175	EBC_BXAP_WBF_ENCODE(0)\| EBC_BXAP_TH_ENCODE(1) \|
176	EBC_BXAP_RE_DISABLED \| EBC_BXAP_BEM_WRITEONLY \|
177	EBC_BXAP_PEN_DISABLED);
178
179	mtebc(pb6cr, EBC_BXCR_BAS_ENCODE(0xF0100000) \|
180	EBC_BXCR_BS_1MB \| EBC_BXCR_BU_RW \| EBC_BXCR_BW_16BIT);
181
182	/*--------------------------------------------------------------------+
183	\| BME-32. Initialize bank 7 with default values.
184	+-------------------------------------------------------------------*/
185	mtebc(pb7ap,
186	EBC_BXAP_RE_ENABLED \| EBC_BXAP_SOR_NONDELAYED \|
187	EBC_BXAP_BME_DISABLED \| EBC_BXAP_TWT_ENCODE(3) \|
188	EBC_BXAP_TH_ENCODE(1) \| EBC_BXAP_WBF_ENCODE(0) \|
189	EBC_BXAP_CSN_ENCODE(1) \| EBC_BXAP_PEN_DISABLED \|
190	EBC_BXAP_OEN_ENCODE(1) \| EBC_BXAP_BEM_RW);
191
192	mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48500000) \|
193	EBC_BXCR_BS_1MB \| EBC_BXCR_BU_RW \| EBC_BXCR_BW_32BIT);
194
b79316f2 SR	195	/*--------------------------------------------------------------------+
	196	* Setup the interrupt controller polarities, triggers, etc.
	197	+-------------------------------------------------------------------*/
	198	mtdcr (uic0sr, 0xffffffff); /* clear all */
	199	mtdcr (uic0er, 0x00000000); /* disable all */
	200	mtdcr (uic0cr, 0x00000000); /* all non- critical */
	201	mtdcr (uic0pr, 0xfffffe03); /* polarity */
	202	mtdcr (uic0tr, 0x01c00000); /* trigger edge vs level */
	203	mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
	204	mtdcr (uic0sr, 0xffffffff); /* clear all */
	205
	206	mtdcr (uic1sr, 0xffffffff); /* clear all */
	207	mtdcr (uic1er, 0x00000000); /* disable all */
	208	mtdcr (uic1cr, 0x00000000); /* all non-critical */
	209	mtdcr (uic1pr, 0xffffc8ff); /* polarity */
	210	mtdcr (uic1tr, 0x00ff0000); /* trigger edge vs level */
	211	mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
	212	mtdcr (uic1sr, 0xffffffff); /* clear all */
	213
	214	mtdcr (uic2sr, 0xffffffff); /* clear all */
	215	mtdcr (uic2er, 0x00000000); /* disable all */
	216	mtdcr (uic2cr, 0x00000000); /* all non-critical */
	217	mtdcr (uic2pr, 0xffff83ff); /* polarity */
	218	mtdcr (uic2tr, 0x00ff8c0f); /* trigger edge vs level */
	219	mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
	220	mtdcr (uic2sr, 0xffffffff); /* clear all */
	221
	222	mtdcr (uicb0sr, 0xfc000000); /* clear all */
	223	mtdcr (uicb0er, 0x00000000); /* disable all */
	224	mtdcr (uicb0cr, 0x00000000); /* all non-critical */
	225	mtdcr (uicb0pr, 0xfc000000);
	226	mtdcr (uicb0tr, 0x00000000);
	227	mtdcr (uicb0vr, 0x00000001);
	228
	229	fpga_init();
	230
	231	return 0;
	232	}
	233
	234
	235	/*************************************************************************
	236	* checkboard
	237	*
	238	* Dump pertinent info to the console
b79316f2 SR	239	************************************************************************/
	240	int checkboard (void)
	241	{
	242	sys_info_t sysinfo;
	243	unsigned char brd_rev, brd_id;
	244	unsigned short sernum;
2b792afc	245	unsigned char scan_rev, scan_id, ofem_rev=0, ofem_id=0;
b79316f2 SR	246	unsigned char ofem_brd_rev, ofem_brd_id;
	247	KAREF_FPGA_REGS_ST *karef_ps;
	248	OFEM_FPGA_REGS_ST *ofem_ps;
	249
	250	karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
	251	ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE;
	252
	253	scan_id = (unsigned char)((karef_ps->revision_ul &
	254	SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK)
	255	>> SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_SHIFT);
	256
	257	scan_rev = (unsigned char)((karef_ps->revision_ul & SAND_HAL_KA_SC_SCAN_REVISION_REVISION_MASK)
	258	>> SAND_HAL_KA_SC_SCAN_REVISION_REVISION_SHIFT);
	259
	260	brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_MASK)
	261	>> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_REV_SHIFT);
	262
	263	brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_MASK)
	264	>> SAND_HAL_KA_SC_SCAN_BRD_INFO_BRD_ID_SHIFT);
	265
	266	ofem_brd_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK)
	267	>> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT);
	268
	269	ofem_brd_rev = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_MASK)
	270	>> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_REV_SHIFT);
	271
	272	if (0xF != ofem_brd_id) {
	273	ofem_id = (unsigned char)((ofem_ps->revision_ul &
	274	SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_MASK)
	275	>> SAND_HAL_KA_OF_OFEM_REVISION_IDENTIFICATION_SHIFT);
	276
	277	ofem_rev = (unsigned char)((ofem_ps->revision_ul &
	278	SAND_HAL_KA_OF_OFEM_REVISION_REVISION_MASK)
	279	>> SAND_HAL_KA_OF_OFEM_REVISION_REVISION_SHIFT);
	280	}
	281
	282	get_sys_info (&sysinfo);
	283
	284	sernum = sbcommon_get_serial_number();
	285
	286	printf ("Board: Sandburst Corporation Kamino Reference Design "
	287	"Serial Number: %d\n", sernum);
	288	printf ("%s\n", KAREF_U_BOOT_REL_STR);
	289
	290	printf ("Built %s %s by %s\n", __DATE__, __TIME__, BUILDUSER);
	291	if (sbcommon_get_master()) {
	292	printf("Slot 0 - Master\nSlave board");
	293	if (sbcommon_secondary_present())
	294	printf(" present\n");
	295	else
	296	printf(" not detected\n");
	297	} else {
	298	printf("Slot 1 - Slave\n\n");
	299	}
	300
	301	printf ("ScanFPGA ID:\t0x%02X\tRev: 0x%02X\n", scan_id, scan_rev);
	302	printf ("Board Rev:\t0x%02X\tID: 0x%02X\n", brd_rev, brd_id);
	303	if(0xF != ofem_brd_id) {
	304	printf("OFemFPGA ID:\t0x%02X\tRev: 0x%02X\n", ofem_id, ofem_rev);
	305	printf("OFEM Board Rev:\t0x%02X\tID: 0x%02X\n", ofem_brd_id, ofem_brd_rev);
	306	}
	307
b79316f2 SR	308	/* Fix the ack in the bme 32 */
	309	udelay(5000);
	310	out32(CFG_BME32_BASE + 0x0000000C, 0x00000001);
	311	asm("eieio");
	312
	313
	314	return (0);
	315	}
	316
b79316f2 SR	317	/*************************************************************************
	318	* misc_init_f
	319	*
	320	* Initialize I2C bus one to gain access to the fans
b79316f2 SR	321	************************************************************************/
	322	int misc_init_f (void)
	323	{
	324	/* Turn on i2c bus 1 */
	325	puts ("I2C1: ");
	326	i2c1_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
	327	puts ("ready\n");
	328
	329	/* Turn on fans 3 & 4 */
	330	sbcommon_fans();
	331
	332	return (0);
	333	}
3d078ce6	334
b79316f2 SR	335	/*************************************************************************
	336	* misc_init_r
	337	*
	338	* Do nothing.
b79316f2 SR	339	************************************************************************/
	340	int misc_init_r (void)
	341	{
	342	unsigned short sernum;
	343	char envstr[255];
	344	KAREF_FPGA_REGS_ST *karef_ps;
	345	OFEM_FPGA_REGS_ST *ofem_ps;
b79316f2 SR	346
	347	if(NULL != getenv("secondserial")) {
	348	puts("secondserial is set, switching to second serial port\n");
	349	setenv("stderr", "serial1");
	350	setenv("stdout", "serial1");
	351	setenv("stdin", "serial1");
	352	}
	353
	354	setenv("ubrelver", KAREF_U_BOOT_REL_STR);
	355
	356	memset(envstr, 0, 255);
	357	sprintf (envstr, "Built %s %s by %s", __DATE__, __TIME__, BUILDUSER);
	358	setenv("bldstr", envstr);
	359	saveenv();
	360
	361	if( getenv("autorecover")) {
	362	setenv("autorecover", NULL);
	363	saveenv();
	364	sernum = sbcommon_get_serial_number();
	365
	366	printf("\nSetting up environment for automatic filesystem recovery\n");
	367	/*
	368	* Setup default bootargs
	369	*/
	370	memset(envstr, 0, 255);
	371
	372	sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
	373	"rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33",
	374	sernum, sernum);
	375	setenv("bootargs", envstr);
	376
	377	/*
	378	* Setup Default boot command
	379	*/
	380	setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;"
	381	"fatload ide 0 8100000 pramdisk;"
	382	"bootm 8000000 8100000");
	383
	384	printf("Done. Please type allow the system to continue to boot\n");
	385	}
	386
	387	if( getenv("fakeled")) {
	388	karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
	389	ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE;
	390	ofem_ps->control_ul &= ~SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK;
	391	karef_ps->control_ul &= ~SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK;
	392	setenv("bootdelay", "-1");
	393	saveenv();
	394	printf("fakeled is set. use 'setenv fakeled ; setenv bootdelay 5 ; saveenv' to recover\n");
	395	}
	396
b79316f2 SR	397	return (0);
	398	}
	399
b79316f2 SR	400	/*************************************************************************
b79316f2 SR	401	* ide_set_reset
b79316f2 SR	402	************************************************************************/
	403	#ifdef CONFIG_IDE_RESET
	404	void ide_set_reset(int on)
	405	{
	406	KAREF_FPGA_REGS_ST *karef_ps;
	407	/* TODO: ide reset */
	408	karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
	409
	410	if (on) {
	411	karef_ps->reset_ul &= ~SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
	412	} else {
	413	karef_ps->reset_ul \|= SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
	414	}
	415	}
	416	#endif /* CONFIG_IDE_RESET */
	417
	418	/*************************************************************************
	419	* fpga_init
b79316f2 SR	420	************************************************************************/
	421	void fpga_init(void)
	422	{
	423	KAREF_FPGA_REGS_ST *karef_ps;
	424	OFEM_FPGA_REGS_ST *ofem_ps;
	425	unsigned char ofem_id;
	426	unsigned long tmp;
	427
	428	/* Ensure we have power all around */
	429	udelay(500);
	430
	431	karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
	432	tmp =
	433	SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK \|
	434	SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK \|
	435	SAND_HAL_KA_SC_SCAN_RESET_KA_RESET_N_MASK \|
	436	SAND_HAL_KA_SC_SCAN_RESET_SLAVE_RESET_N_MASK \|
	437	SAND_HAL_KA_SC_SCAN_RESET_OFEM_RESET_N_MASK \|
	438	SAND_HAL_KA_SC_SCAN_RESET_IFE_A_RESET_N_MASK \|
	439	SAND_HAL_KA_SC_SCAN_RESET_I2C_MUX1_RESET_N_MASK \|
	440	SAND_HAL_KA_SC_SCAN_RESET_PHY0_RESET_N_MASK \|
	441	SAND_HAL_KA_SC_SCAN_RESET_PHY1_RESET_N_MASK;
	442
	443	karef_ps->reset_ul = tmp;
	444
	445	/*
	446	* Wait a bit to allow the ofem fpga to get its brains
	447	*/
	448	udelay(5000);
	449
	450	/*
	451	* Check to see if the ofem is there
	452	*/
	453	ofem_id = (unsigned char)((karef_ps->boardinfo_ul & SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_MASK)
	454	>> SAND_HAL_KA_SC_SCAN_BRD_INFO_FEM_ID_SHIFT);
	455	if(0xF != ofem_id) {
	456	tmp =
	457	SAND_HAL_KA_OF_OFEM_RESET_I2C_MUX0_RESET_N_MASK \|
	458	SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK \|
	459	SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK;
	460
	461	ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE;
	462	ofem_ps->reset_ul = tmp;
	463
	464	ofem_ps->control_ul \|= 1 < SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT;
	465	}
	466
	467	karef_ps->control_ul \|= 1 << SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_SHIFT;
	468
	469	asm("eieio");
	470
	471	return;
	472	}
	473
b79316f2 SR	474	int karefSetupVars(cmd_tbl_t cmdtp, int flag, int argc, char argv[])
	475	{
	476	unsigned short sernum;
	477	char envstr[255];
	478
	479	sernum = sbcommon_get_serial_number();
	480
	481	memset(envstr, 0, 255);
	482	/*
	483	* Setup our ip address
	484	*/
	485	sprintf(envstr, "10.100.70.%d", sernum);
	486
	487	setenv("ipaddr", envstr);
	488	/*
	489	* Setup the host ip address
	490	*/
	491	setenv("serverip", "10.100.17.10");
	492
	493	/*
	494	* Setup default bootargs
	495	*/
	496	memset(envstr, 0, 255);
	497
	498	sprintf(envstr, "console=ttyS0,9600 root=/dev/nfs "
	499	"rw nfsroot=10.100.17.10:/home/metrobox/mbc70.%d "
	500	"nfsaddrs=10.100.70.%d:10.100.17.10:10.100.1.1:"
	501	"255.255.0.0:karef%d.sandburst.com:eth0:none idebus=33",
	502	sernum, sernum, sernum);
	503
	504	setenv("bootargs_nfs", envstr);
	505	setenv("bootargs", envstr);
	506
	507	/*
	508	* Setup CF bootargs
	509	*/
	510	memset(envstr, 0, 255);
	511
	512	sprintf(envstr, "console=ttyS0,9600 root=/dev/hda2 "
	513	"rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none idebus=33",
	514	sernum, sernum);
	515
	516	setenv("bootargs_cf", envstr);
	517
	518	/*
	519	* Setup Default boot command
	520	*/
	521	setenv("bootcmd_tftp", "tftp 8000000 uImage.karef;bootm 8000000");
	522	setenv("bootcmd", "tftp 8000000 uImage.karef;bootm 8000000");
	523
	524	/*
	525	* Setup compact flash boot command
	526	*/
	527	setenv("bootcmd_cf", "fatload ide 0 8000000 uimage.karef;bootm 8000000");
	528
	529	saveenv();
	530
	531	return(1);
	532	}
	533
b79316f2 SR	534	int karefRecover(cmd_tbl_t cmdtp, int flag, int argc, char argv[])
	535	{
	536	unsigned short sernum;
	537	char envstr[255];
	538
	539	sernum = sbcommon_get_serial_number();
	540
	541	printf("\nSetting up environment for filesystem recovery\n");
	542	/*
	543	* Setup default bootargs
	544	*/
	545	memset(envstr, 0, 255);
	546
	547	sprintf(envstr, "console=ttyS0,9600 root=/dev/ram0 "
	548	"rw ip=10.100.70.%d:::255.255.0.0:karef%d:eth0:none",
	549	sernum, sernum);
	550	setenv("bootargs", envstr);
	551
	552	/*
	553	* Setup Default boot command
	554	*/
	555
	556	setenv("bootcmd", "fatload ide 0 8000000 uimage.karef;"
	557	"fatload ide 0 8100000 pramdisk;"
	558	"bootm 8000000 8100000");
	559
	560	printf("Done. Please type boot<cr>.\nWhen the kernel has booted"
	561	" please type fsrecover.sh<cr>\n");
	562
	563	return(1);
	564	}
	565
b79316f2 SR	566	U_BOOT_CMD(kasetup, 1, 1, karefSetupVars,
	567	"kasetup - Set environment to factory defaults\n", NULL);
	568
	569	U_BOOT_CMD(karecover, 1, 1, karefRecover,
	570	"karecover - Set environment to allow for fs recovery\n", NULL);