Merge tag 'x86_microcode_update_for_v5.11' of git://git.kernel.org/pub/scm/linux...

[J-linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_debugfs.c

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index 8ec4806c2ff40f3ca8d79bf21f3402efae81c667..a6667a2ca0db3997f9a37de68d3a6fac19048824 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -35,6 +35,7 @@
 #include "amdgpu_dm_debugfs.h"
 #include "amdgpu_ras.h"
 #include "amdgpu_rap.h"
+#include "amdgpu_fw_attestation.h"
 
 /**
  * amdgpu_debugfs_add_files - Add simple debugfs entries
@@ -169,14 +170,14 @@ static void amdgpu_debugfs_autodump_init(struct amdgpu_device *adev)
  *
  * Bit 62:  Indicates a GRBM bank switch is needed
  * Bit 61:  Indicates a SRBM bank switch is needed (implies bit 62 is
- *                     zero)
+ *         zero)
  * Bits 24..33: The SE or ME selector if needed
  * Bits 34..43: The SH (or SA) or PIPE selector if needed
  * Bits 44..53: The INSTANCE (or CU/WGP) or QUEUE selector if needed
  *
  * Bit 23:  Indicates that the PM power gating lock should be held
- *                     This is necessary to read registers that might be
- *                     unreliable during a power gating transistion.
+ *         This is necessary to read registers that might be
+ *         unreliable during a power gating transistion.
  *
  * The lower bits are the BYTE offset of the register to read.  This
  * allows reading multiple registers in a single call and having
@@ -299,7 +300,7 @@ end:
        return result;
 }
 
-/**
+/*
  * amdgpu_debugfs_regs_read - Callback for reading MMIO registers
  */
 static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
@@ -308,7 +309,7 @@ static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
        return amdgpu_debugfs_process_reg_op(true, f, buf, size, pos);
 }
 
-/**
+/*
  * amdgpu_debugfs_regs_write - Callback for writing MMIO registers
  */
 static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
@@ -864,7 +865,7 @@ static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
 {
        struct amdgpu_device *adev = f->f_inode->i_private;
        int r, x;
-       ssize_t result=0;
+       ssize_t result = 0;
        uint32_t offset, se, sh, cu, wave, simd, data[32];
 
        if (size & 3 || *pos & 3)
@@ -1210,7 +1211,7 @@ static const char *debugfs_regs_names[] = {
 
 /**
  * amdgpu_debugfs_regs_init -  Initialize debugfs entries that provide
- *                                                             register access.
+ *                             register access.
  *
  * @adev: The device to attach the debugfs entries to
  */
@@ -1319,6 +1320,7 @@ static int amdgpu_debugfs_evict_gtt(struct seq_file *m, void *data)
        struct drm_info_node *node = (struct drm_info_node *)m->private;
        struct drm_device *dev = node->minor->dev;
        struct amdgpu_device *adev = drm_to_adev(dev);
+       struct ttm_resource_manager *man;
        int r;
 
        r = pm_runtime_get_sync(dev->dev);
@@ -1327,7 +1329,9 @@ static int amdgpu_debugfs_evict_gtt(struct seq_file *m, void *data)
                return r;
        }
 
-       seq_printf(m, "(%d)\n", ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_TT));
+       man = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT);
+       r = ttm_resource_manager_evict_all(&adev->mman.bdev, man);
+       seq_printf(m, "(%d)\n", r);
 
        pm_runtime_mark_last_busy(dev->dev);
        pm_runtime_put_autosuspend(dev->dev);
@@ -1665,6 +1669,8 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev)
 
        amdgpu_rap_debugfs_init(adev);
 
+       amdgpu_fw_attestation_debugfs_init(adev);
+
        return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_list,
                                        ARRAY_SIZE(amdgpu_debugfs_list));
 }