Merge tag 'rpmsg-v5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/andersson...

[J-linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_device.c

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 0471a1d4305c3a40cf76a51b4fc0131c0e29a480..5a1939dbd4e3e6785066854f4224f6ffe881f7fd 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -71,6 +71,7 @@ MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
 MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
 MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
 MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin");
+MODULE_FIRMWARE("amdgpu/renoir_gpu_info.bin");
 MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin");
 MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin");
 MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
@@ -102,6 +103,7 @@ static const char *amdgpu_asic_name[] = {
        "VEGA20",
        "RAVEN",
        "ARCTURUS",
+       "RENOIR",
        "NAVI10",
        "NAVI14",
        "NAVI12",
@@ -263,39 +265,6 @@ void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
        }
 }
 
-/**
- * amdgpu_mm_rreg64 - read a 64 bit memory mapped IO register
- *
- * @adev: amdgpu_device pointer
- * @reg: dword aligned register offset
- *
- * Returns the 64 bit value from the offset specified.
- */
-uint64_t amdgpu_mm_rreg64(struct amdgpu_device *adev, uint32_t reg)
-{
-       if ((reg * 4) < adev->rmmio_size)
-               return atomic64_read((atomic64_t *)(adev->rmmio + (reg * 4)));
-       else
-               BUG();
-}
-
-/**
- * amdgpu_mm_wreg64 - write to a 64 bit memory mapped IO register
- *
- * @adev: amdgpu_device pointer
- * @reg: dword aligned register offset
- * @v: 64 bit value to write to the register
- *
- * Writes the value specified to the offset specified.
- */
-void amdgpu_mm_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)
-{
-       if ((reg * 4) < adev->rmmio_size)
-               atomic64_set((atomic64_t *)(adev->rmmio + (reg * 4)), v);
-       else
-               BUG();
-}
-
 /**
  * amdgpu_io_rreg - read an IO register
  *
@@ -1460,6 +1429,9 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
        case CHIP_ARCTURUS:
                chip_name = "arcturus";
                break;
+       case CHIP_RENOIR:
+               chip_name = "renoir";
+               break;
        case CHIP_NAVI10:
                chip_name = "navi10";
                break;
@@ -1612,7 +1584,9 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
        case CHIP_VEGA20:
        case CHIP_RAVEN:
        case CHIP_ARCTURUS:
-               if (adev->asic_type == CHIP_RAVEN)
+       case CHIP_RENOIR:
+               if (adev->asic_type == CHIP_RAVEN ||
+                   adev->asic_type == CHIP_RENOIR)
                        adev->family = AMDGPU_FAMILY_RV;
                else
                        adev->family = AMDGPU_FAMILY_AI;
@@ -2544,6 +2518,9 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
        case CHIP_NAVI10:
        case CHIP_NAVI14:
        case CHIP_NAVI12:
+#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+       case CHIP_RENOIR:
 #endif
                return amdgpu_dc != 0;
 #endif
@@ -3509,7 +3486,7 @@ error:
        amdgpu_virt_init_data_exchange(adev);
        amdgpu_virt_release_full_gpu(adev, true);
        if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
-               atomic_inc(&adev->vram_lost_counter);
+               amdgpu_inc_vram_lost(adev);
                r = amdgpu_device_recover_vram(adev);
        }
 
@@ -3551,6 +3528,7 @@ bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
                case CHIP_VEGA20:
                case CHIP_VEGA10:
                case CHIP_VEGA12:
+               case CHIP_RAVEN:
                        break;
                default:
                        goto disabled;
@@ -3674,7 +3652,7 @@ static int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive,
                                vram_lost = amdgpu_device_check_vram_lost(tmp_adev);
                                if (vram_lost) {
                                        DRM_INFO("VRAM is lost due to GPU reset!\n");
-                                       atomic_inc(&tmp_adev->vram_lost_counter);
+                                       amdgpu_inc_vram_lost(tmp_adev);
                                }
 
                                r = amdgpu_gtt_mgr_recover(
@@ -3816,14 +3794,14 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
 
        if (hive && !mutex_trylock(&hive->reset_lock)) {
                DRM_INFO("Bailing on TDR for s_job:%llx, hive: %llx as another already in progress",
-                        job->base.id, hive->hive_id);
+                         job ? job->base.id : -1, hive->hive_id);
                return 0;
        }
 
        /* Start with adev pre asic reset first for soft reset check.*/
        if (!amdgpu_device_lock_adev(adev, !hive)) {
                DRM_INFO("Bailing on TDR for s_job:%llx, as another already in progress",
-                                        job->base.id);
+                         job ? job->base.id : -1);
                return 0;
        }
 
@@ -3864,7 +3842,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
                        if (!ring || !ring->sched.thread)
                                continue;
 
-                       drm_sched_stop(&ring->sched, &job->base);
+                       drm_sched_stop(&ring->sched, job ? &job->base : NULL);
                }
        }
 
@@ -3889,9 +3867,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev,
 
 
        /* Guilty job will be freed after this*/
-       r = amdgpu_device_pre_asic_reset(adev,
-                                        job,
-                                        &need_full_reset);
+       r = amdgpu_device_pre_asic_reset(adev, job, &need_full_reset);
        if (r) {
                /*TODO Should we stop ?*/
                DRM_ERROR("GPU pre asic reset failed with err, %d for drm dev, %s ",