Merge tag 'drm-misc-next-fixes-2023-11-02' of git://anongit.freedesktop.org/drm/drm...

[J-linux.git] / drivers / gpu / drm / amd / amdgpu / psp_v13_0.c

diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
index 10b17bd5aebe501ae1b61f603a6f3ba12e21099f..4142e2fcd8667571d34649dfb26e2c29431c9bad 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
@@ -59,6 +59,9 @@ MODULE_FIRMWARE("amdgpu/psp_14_0_0_ta.bin");
 /* Read USB-PD from LFB */
 #define GFX_CMD_USB_PD_USE_LFB 0x480
 
+/* Retry times for vmbx ready wait */
+#define PSP_VMBX_POLLING_LIMIT 20000
+
 /* VBIOS gfl defines */
 #define MBOX_READY_MASK 0x80000000
 #define MBOX_STATUS_MASK 0x0000FFFF
@@ -79,7 +82,7 @@ static int psp_v13_0_init_microcode(struct psp_context *psp)
 
        amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
 
-       switch (adev->ip_versions[MP0_HWIP][0]) {
+       switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
        case IP_VERSION(13, 0, 2):
                err = psp_init_sos_microcode(psp, ucode_prefix);
                if (err)
@@ -133,19 +136,39 @@ static bool psp_v13_0_is_sos_alive(struct psp_context *psp)
        return sol_reg != 0x0;
 }
 
-static int psp_v13_0_wait_for_bootloader(struct psp_context *psp)
+static int psp_v13_0_wait_for_vmbx_ready(struct psp_context *psp)
 {
        struct amdgpu_device *adev = psp->adev;
+       int retry_loop, ret;
 
-       int ret;
-       int retry_loop;
+       for (retry_loop = 0; retry_loop < PSP_VMBX_POLLING_LIMIT; retry_loop++) {
+               /* Wait for bootloader to signify that is
+                  ready having bit 31 of C2PMSG_33 set to 1 */
+               ret = psp_wait_for(
+                       psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_33),
+                       0x80000000, 0xffffffff, false);
+
+               if (ret == 0)
+                       break;
+       }
+
+       if (ret)
+               dev_warn(adev->dev, "Bootloader wait timed out");
+
+       return ret;
+}
+
+static int psp_v13_0_wait_for_bootloader(struct psp_context *psp)
+{
+       struct amdgpu_device *adev = psp->adev;
+       int retry_loop, ret;
 
        /* Wait for bootloader to signify that it is ready having bit 31 of
         * C2PMSG_35 set to 1. All other bits are expected to be cleared.
         * If there is an error in processing command, bits[7:0] will be set.
         * This is applicable for PSP v13.0.6 and newer.
         */
-       for (retry_loop = 0; retry_loop < 10; retry_loop++) {
+       for (retry_loop = 0; retry_loop < PSP_VMBX_POLLING_LIMIT; retry_loop++) {
                ret = psp_wait_for(
                        psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
                        0x80000000, 0xffffffff, false);
@@ -157,6 +180,19 @@ static int psp_v13_0_wait_for_bootloader(struct psp_context *psp)
        return ret;
 }
 
+static int psp_v13_0_wait_for_bootloader_steady_state(struct psp_context *psp)
+{
+       struct amdgpu_device *adev = psp->adev;
+
+       if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6)) {
+               psp_v13_0_wait_for_vmbx_ready(psp);
+
+               return psp_v13_0_wait_for_bootloader(psp);
+       }
+
+       return 0;
+}
+
 static int psp_v13_0_bootloader_load_component(struct psp_context      *psp,
                                               struct psp_bin_desc      *bin_desc,
                                               enum psp_bootloader_cmd  bl_cmd)
@@ -227,6 +263,12 @@ static int psp_v13_0_bootloader_load_ras_drv(struct psp_context *psp)
        return psp_v13_0_bootloader_load_component(psp, &psp->ras_drv, PSP_BL__LOAD_RASDRV);
 }
 
+static inline void psp_v13_0_init_sos_version(struct psp_context *psp)
+{
+       struct amdgpu_device *adev = psp->adev;
+
+       psp->sos.fw_version = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_58);
+}
 
 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp)
 {
@@ -237,8 +279,10 @@ static int psp_v13_0_bootloader_load_sos(struct psp_context *psp)
        /* Check sOS sign of life register to confirm sys driver and sOS
         * are already been loaded.
         */
-       if (psp_v13_0_is_sos_alive(psp))
+       if (psp_v13_0_is_sos_alive(psp)) {
+               psp_v13_0_init_sos_version(psp);
                return 0;
+       }
 
        ret = psp_v13_0_wait_for_bootloader(psp);
        if (ret)
@@ -262,6 +306,9 @@ static int psp_v13_0_bootloader_load_sos(struct psp_context *psp)
                           RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81),
                           0, true);
 
+       if (!ret)
+               psp_v13_0_init_sos_version(psp);
+
        return ret;
 }
 
@@ -695,7 +742,7 @@ static int psp_v13_0_fatal_error_recovery_quirk(struct psp_context *psp)
 {
        struct amdgpu_device *adev = psp->adev;
 
-       if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 10)) {
+       if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 10)) {
                uint32_t  reg_data;
                /* MP1 fatal error: trigger PSP dram read to unhalt PSP
                 * during MP1 triggered sync flood.
@@ -714,6 +761,7 @@ static int psp_v13_0_fatal_error_recovery_quirk(struct psp_context *psp)
 
 static const struct psp_funcs psp_v13_0_funcs = {
        .init_microcode = psp_v13_0_init_microcode,
+       .wait_for_bootloader = psp_v13_0_wait_for_bootloader_steady_state,
        .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb,
        .bootloader_load_spl = psp_v13_0_bootloader_load_spl,
        .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv,