MODULE_FIRMWARE("amdgpu/picasso_gpu_info.bin");
MODULE_FIRMWARE("amdgpu/raven2_gpu_info.bin");
MODULE_FIRMWARE("amdgpu/arcturus_gpu_info.bin");
+MODULE_FIRMWARE("amdgpu/renoir_gpu_info.bin");
MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin");
MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin");
MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
"VEGA20",
"RAVEN",
"ARCTURUS",
+ "RENOIR",
"NAVI10",
"NAVI14",
"NAVI12",
}
}
-/**
- * amdgpu_mm_rreg64 - read a 64 bit memory mapped IO register
- *
- * @adev: amdgpu_device pointer
- * @reg: dword aligned register offset
- *
- * Returns the 64 bit value from the offset specified.
- */
-uint64_t amdgpu_mm_rreg64(struct amdgpu_device *adev, uint32_t reg)
-{
- uint64_t ret;
-
- if ((reg * 4) < adev->rmmio_size)
- ret = readq(((void __iomem *)adev->rmmio) + (reg * 4));
- else
- BUG();
-
- return ret;
-}
-
-/**
- * amdgpu_mm_wreg64 - write to a 64 bit memory mapped IO register
- *
- * @adev: amdgpu_device pointer
- * @reg: dword aligned register offset
- * @v: 64 bit value to write to the register
- *
- * Writes the value specified to the offset specified.
- */
-void amdgpu_mm_wreg64(struct amdgpu_device *adev, uint32_t reg, uint64_t v)
-{
- if ((reg * 4) < adev->rmmio_size)
- writeq(v, ((void __iomem *)adev->rmmio) + (reg * 4));
- else
- BUG();
-}
-
/**
* amdgpu_io_rreg - read an IO register
*
case CHIP_ARCTURUS:
chip_name = "arcturus";
break;
+ case CHIP_RENOIR:
+ chip_name = "renoir";
+ break;
case CHIP_NAVI10:
chip_name = "navi10";
break;
case CHIP_VEGA20:
case CHIP_RAVEN:
case CHIP_ARCTURUS:
- if (adev->asic_type == CHIP_RAVEN)
+ case CHIP_RENOIR:
+ if (adev->asic_type == CHIP_RAVEN ||
+ adev->asic_type == CHIP_RENOIR)
adev->family = AMDGPU_FAMILY_RV;
else
adev->family = AMDGPU_FAMILY_AI;
case CHIP_NAVI10:
case CHIP_NAVI14:
case CHIP_NAVI12:
+#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ case CHIP_RENOIR:
#endif
return amdgpu_dc != 0;
#endif
amdgpu_virt_init_data_exchange(adev);
amdgpu_virt_release_full_gpu(adev, true);
if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
- atomic_inc(&adev->vram_lost_counter);
+ amdgpu_inc_vram_lost(adev);
r = amdgpu_device_recover_vram(adev);
}
case CHIP_VEGA20:
case CHIP_VEGA10:
case CHIP_VEGA12:
+ case CHIP_RAVEN:
break;
default:
goto disabled;
vram_lost = amdgpu_device_check_vram_lost(tmp_adev);
if (vram_lost) {
DRM_INFO("VRAM is lost due to GPU reset!\n");
- atomic_inc(&tmp_adev->vram_lost_counter);
+ amdgpu_inc_vram_lost(tmp_adev);
}
r = amdgpu_gtt_mgr_recover(
if (hive && !mutex_trylock(&hive->reset_lock)) {
DRM_INFO("Bailing on TDR for s_job:%llx, hive: %llx as another already in progress",
- job->base.id, hive->hive_id);
+ job ? job->base.id : -1, hive->hive_id);
return 0;
}
/* Start with adev pre asic reset first for soft reset check.*/
if (!amdgpu_device_lock_adev(adev, !hive)) {
DRM_INFO("Bailing on TDR for s_job:%llx, as another already in progress",
- job->base.id);
+ job ? job->base.id : -1);
return 0;
}
if (!ring || !ring->sched.thread)
continue;
- drm_sched_stop(&ring->sched, &job->base);
+ drm_sched_stop(&ring->sched, job ? &job->base : NULL);
}
}
/* Guilty job will be freed after this*/
- r = amdgpu_device_pre_asic_reset(adev,
- job,
- &need_full_reset);
+ r = amdgpu_device_pre_asic_reset(adev, job, &need_full_reset);
if (r) {
/*TODO Should we stop ?*/
DRM_ERROR("GPU pre asic reset failed with err, %d for drm dev, %s ",