regmap_write(priv->regmap, TIM_PSC, prescaler);
regmap_write(priv->regmap, TIM_ARR, prd - 1);
regmap_write(priv->regmap, TIM_PSC, prescaler);
regmap_write(priv->regmap, TIM_ARR, prd - 1);
- regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
+ regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE);
- regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
+ regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);
- regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
+ regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
- regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
- regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
+ regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE);
+ regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
regmap_write(priv->regmap, TIM_PSC, 0);
regmap_write(priv->regmap, TIM_ARR, 0);
/* Force disable master mode */
if (stm32_timer_is_trgo2_name(trig->name))
regmap_write(priv->regmap, TIM_PSC, 0);
regmap_write(priv->regmap, TIM_ARR, 0);
/* Force disable master mode */
if (stm32_timer_is_trgo2_name(trig->name))
- regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 0);
+ regmap_clear_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2);
- regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS, 0);
+ regmap_clear_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS);
- regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
+ regmap_set_bits(priv->regmap, TIM_EGR, TIM_EGR_UG);
- regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,
- TIM_CR1_CEN);
+ regmap_set_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
- regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,
- 0);
+ regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
- regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, TIM_SMCR_SMS);
+ regmap_set_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS);
- regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
+ regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE);
- regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, TIM_CR2_MMS2);
+ regmap_set_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2);
- regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 0);
+ regmap_clear_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2);
/* Check if nobody else use the timer, then disable it */
regmap_read(priv->regmap, TIM_CCER, &val);
if (!(val & TIM_CCER_CCXE))
/* Check if nobody else use the timer, then disable it */
regmap_read(priv->regmap, TIM_CCER, &val);
if (!(val & TIM_CCER_CCXE))
- regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
+ regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
- regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
+ regmap_clear_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN);
static struct platform_driver stm32_timer_trigger_driver = {
.probe = stm32_timer_trigger_probe,
static struct platform_driver stm32_timer_trigger_driver = {
.probe = stm32_timer_trigger_probe,
.driver = {
.name = "stm32-timer-trigger",
.of_match_table = stm32_trig_of_match,
.driver = {
.name = "stm32-timer-trigger",
.of_match_table = stm32_trig_of_match,