drm/amdgpu: drm_device to amdgpu_device by inline-f (v2)

[J-linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ucode.c

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
index cf3438696fcecd86b6361527e9c2ea0c58c6d622..55fe19a2f332276b5ef1d581b43c7e4db4909444 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
@@ -279,6 +279,30 @@ void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr)
                        DRM_DEBUG("kdb_size_bytes: %u\n",
                                  le32_to_cpu(psp_hdr_v1_2->kdb_size_bytes));
                }
+               if (version_minor == 3) {
+                       const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 =
+                               container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0);
+                       const struct psp_firmware_header_v1_3 *psp_hdr_v1_3 =
+                               container_of(psp_hdr_v1_1, struct psp_firmware_header_v1_3, v1_1);
+                       DRM_DEBUG("toc_header_version: %u\n",
+                                 le32_to_cpu(psp_hdr_v1_3->v1_1.toc_header_version));
+                       DRM_DEBUG("toc_offset_bytes: %u\n",
+                                 le32_to_cpu(psp_hdr_v1_3->v1_1.toc_offset_bytes));
+                       DRM_DEBUG("toc_size_bytes: %u\n",
+                                 le32_to_cpu(psp_hdr_v1_3->v1_1.toc_size_bytes));
+                       DRM_DEBUG("kdb_header_version: %u\n",
+                                 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb_header_version));
+                       DRM_DEBUG("kdb_offset_bytes: %u\n",
+                                 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb_offset_bytes));
+                       DRM_DEBUG("kdb_size_bytes: %u\n",
+                                 le32_to_cpu(psp_hdr_v1_3->v1_1.kdb_size_bytes));
+                       DRM_DEBUG("spl_header_version: %u\n",
+                                 le32_to_cpu(psp_hdr_v1_3->spl_header_version));
+                       DRM_DEBUG("spl_offset_bytes: %u\n",
+                                 le32_to_cpu(psp_hdr_v1_3->spl_offset_bytes));
+                       DRM_DEBUG("spl_size_bytes: %u\n",
+                                 le32_to_cpu(psp_hdr_v1_3->spl_size_bytes));
+               }
        } else {
                DRM_ERROR("Unknown PSP ucode version: %u.%u\n",
                          version_major, version_minor);
@@ -366,11 +390,11 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
        case CHIP_NAVI14:
        case CHIP_NAVI12:
        case CHIP_SIENNA_CICHLID:
+       case CHIP_NAVY_FLOUNDER:
                if (!load_type)
                        return AMDGPU_FW_LOAD_DIRECT;
                else
                        return AMDGPU_FW_LOAD_PSP;
-
        default:
                DRM_ERROR("Unknown firmware load type\n");
        }
@@ -384,7 +408,7 @@ static ssize_t show_##name(struct device *dev,                              \
                          char *buf)                                    \
 {                                                                      \
        struct drm_device *ddev = dev_get_drvdata(dev);                 \
-       struct amdgpu_device *adev = ddev->dev_private;                 \
+       struct amdgpu_device *adev = drm_to_adev(ddev);                 \
                                                                        \
        return snprintf(buf, PAGE_SIZE, "0x%08x\n", adev->field);       \
 }                                                                      \
@@ -604,7 +628,7 @@ int amdgpu_ucode_init_bo(struct amdgpu_device *adev)
        struct amdgpu_firmware_info *ucode = NULL;
 
  /* for baremetal, the ucode is allocated in gtt, so don't need to fill the bo when reset/suspend */
-       if (!amdgpu_sriov_vf(adev) && (adev->in_gpu_reset || adev->in_suspend))
+       if (!amdgpu_sriov_vf(adev) && (amdgpu_in_reset(adev) || adev->in_suspend))
                return 0;
        /*
         * if SMU loaded firmware, it needn't add SMC, UVD, and VCE