Merge tag 'tag-chrome-platform-for-v5.20' of git://git.kernel.org/pub/scm/linux/kerne...

[J-linux.git] / drivers / gpu / drm / amd / amdgpu / imu_v11_0.c

diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
index d63d3f2b8a161973c08365d839dda693c3810dfb..76383baa3929ac7a2cd56bd3c1533a7b05c84aa3 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c
@@ -24,6 +24,7 @@
 #include <linux/firmware.h>
 #include "amdgpu.h"
 #include "amdgpu_imu.h"
+#include "amdgpu_dpm.h"
 
 #include "gc/gc_11_0_0_offset.h"
 #include "gc/gc_11_0_0_sh_mask.h"
@@ -117,6 +118,25 @@ static int imu_v11_0_load_microcode(struct amdgpu_device *adev)
        return 0;
 }
 
+static int imu_v11_0_wait_for_reset_status(struct amdgpu_device *adev)
+{
+       int i, imu_reg_val = 0;
+
+       for (i = 0; i < adev->usec_timeout; i++) {
+               imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL);
+               if ((imu_reg_val & 0x1f) == 0x1f)
+                       break;
+               udelay(1);
+       }
+
+       if (i >= adev->usec_timeout) {
+               dev_err(adev->dev, "init imu: IMU start timeout\n");
+               return -ETIMEDOUT;
+       }
+
+       return 0;
+}
+
 static void imu_v11_0_setup(struct amdgpu_device *adev)
 {
        int imu_reg_val;
@@ -125,9 +145,11 @@ static void imu_v11_0_setup(struct amdgpu_device *adev)
        WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL0, 0xffffff);
        WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL1, 0xffff);
 
-       imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16);
-       imu_reg_val |= 0x1;
-       WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16, imu_reg_val);
+       if (adev->gfx.imu.mode == DEBUG_MODE) {
+               imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16);
+               imu_reg_val |= 0x1;
+               WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16, imu_reg_val);
+       }
 
        //disble imu Rtavfs, SmsRepair, DfllBTC, and ClkB
        imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10);
@@ -137,26 +159,17 @@ static void imu_v11_0_setup(struct amdgpu_device *adev)
 
 static int imu_v11_0_start(struct amdgpu_device *adev)
 {
-       int imu_reg_val, i;
+       int imu_reg_val;
 
        //Start IMU by set GFX_IMU_CORE_CTRL.CRESET = 0
        imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL);
        imu_reg_val &= 0xfffffffe;
        WREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL, imu_reg_val);
 
-       for (i = 0; i < adev->usec_timeout; i++) {
-               imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL);
-               if ((imu_reg_val & 0x1f) == 0x1f)
-                       break;
-               udelay(1);
-       }
+       if (adev->flags & AMD_IS_APU)
+               amdgpu_dpm_set_gfx_power_up_by_imu(adev);
 
-       if (i >= adev->usec_timeout) {
-               dev_err(adev->dev, "init imu: IMU start timeout\n");
-               return -ETIMEDOUT;
-       }
-
-       return 0;
+       return imu_v11_0_wait_for_reset_status(adev);
 }
 
 static const struct imu_rlc_ram_golden imu_rlc_ram_golden_11[] =
@@ -364,4 +377,5 @@ const struct amdgpu_imu_funcs gfx_v11_0_imu_funcs = {
        .setup_imu = imu_v11_0_setup,
        .start_imu = imu_v11_0_start,
        .program_rlc_ram = imu_v11_0_program_rlc_ram,
+       .wait_for_reset_status = imu_v11_0_wait_for_reset_status,
 };