Merge tag 'vfio-v5.10-rc1' of git://github.com/awilliam/linux-vfio

[J-linux.git] / drivers / gpu / drm / amd / amdgpu / nv.c

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index ca11253e787cac8949d8edd066897bb29f510830..1ce741a0c6a74ce0fe183dfc635e50e9cb0039e9 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -69,75 +69,40 @@ static const struct amd_ip_funcs nv_common_ip_funcs;
  */
 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg)
 {
-       unsigned long flags, address, data;
-       u32 r;
+       unsigned long address, data;
        address = adev->nbio.funcs->get_pcie_index_offset(adev);
        data = adev->nbio.funcs->get_pcie_data_offset(adev);
 
-       spin_lock_irqsave(&adev->pcie_idx_lock, flags);
-       WREG32(address, reg);
-       (void)RREG32(address);
-       r = RREG32(data);
-       spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
-       return r;
+       return amdgpu_device_indirect_rreg(adev, address, data, reg);
 }
 
 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 {
-       unsigned long flags, address, data;
+       unsigned long address, data;
 
        address = adev->nbio.funcs->get_pcie_index_offset(adev);
        data = adev->nbio.funcs->get_pcie_data_offset(adev);
 
-       spin_lock_irqsave(&adev->pcie_idx_lock, flags);
-       WREG32(address, reg);
-       (void)RREG32(address);
-       WREG32(data, v);
-       (void)RREG32(data);
-       spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+       amdgpu_device_indirect_wreg(adev, address, data, reg, v);
 }
 
 static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
 {
-       unsigned long flags, address, data;
-       u64 r;
+       unsigned long address, data;
        address = adev->nbio.funcs->get_pcie_index_offset(adev);
        data = adev->nbio.funcs->get_pcie_data_offset(adev);
 
-       spin_lock_irqsave(&adev->pcie_idx_lock, flags);
-       /* read low 32 bit */
-       WREG32(address, reg);
-       (void)RREG32(address);
-       r = RREG32(data);
-
-       /* read high 32 bit*/
-       WREG32(address, reg + 4);
-       (void)RREG32(address);
-       r |= ((u64)RREG32(data) << 32);
-       spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
-       return r;
+       return amdgpu_device_indirect_rreg64(adev, address, data, reg);
 }
 
 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
 {
-       unsigned long flags, address, data;
+       unsigned long address, data;
 
        address = adev->nbio.funcs->get_pcie_index_offset(adev);
        data = adev->nbio.funcs->get_pcie_data_offset(adev);
 
-       spin_lock_irqsave(&adev->pcie_idx_lock, flags);
-       /* write low 32 bit */
-       WREG32(address, reg);
-       (void)RREG32(address);
-       WREG32(data, (u32)(v & 0xffffffffULL));
-       (void)RREG32(data);
-
-       /* write high 32 bit */
-       WREG32(address, reg + 4);
-       (void)RREG32(address);
-       WREG32(data, (u32)(v >> 32));
-       (void)RREG32(data);
-       spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
+       amdgpu_device_indirect_wreg64(adev, address, data, reg, v);
 }
 
 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)
@@ -311,7 +276,7 @@ static int nv_asic_mode1_reset(struct amdgpu_device *adev)
        /* disable BM */
        pci_clear_master(adev->pdev);
 
-       pci_save_state(adev->pdev);
+       amdgpu_device_cache_pci_state(adev->pdev);
 
        if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
                dev_info(adev->dev, "GPU smu mode1 reset\n");
@@ -323,7 +288,7 @@ static int nv_asic_mode1_reset(struct amdgpu_device *adev)
 
        if (ret)
                dev_err(adev->dev, "GPU mode1 reset failed\n");
-       pci_restore_state(adev->pdev);
+       amdgpu_device_load_pci_state(adev->pdev);
 
        /* wait for asic to come out of reset */
        for (i = 0; i < adev->usec_timeout; i++) {
@@ -380,7 +345,7 @@ static int nv_asic_reset(struct amdgpu_device *adev)
        struct smu_context *smu = &adev->smu;
 
        if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
-               dev_info(adev->dev, "GPU BACO reset\n");
+               dev_info(adev->dev, "BACO reset\n");
 
                ret = smu_baco_enter(smu);
                if (ret)
@@ -388,8 +353,10 @@ static int nv_asic_reset(struct amdgpu_device *adev)
                ret = smu_baco_exit(smu);
                if (ret)
                        return ret;
-       } else
+       } else {
+               dev_info(adev->dev, "MODE1 reset\n");
                ret = nv_asic_mode1_reset(adev);
+       }
 
        return ret;
 }
@@ -619,7 +586,7 @@ static void nv_invalidate_hdp(struct amdgpu_device *adev,
                                struct amdgpu_ring *ring)
 {
        if (!ring || !ring->funcs->emit_wreg) {
-               WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
+               WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
        } else {
                amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
                                        HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
@@ -690,6 +657,10 @@ static void nv_init_doorbell_index(struct amdgpu_device *adev)
        adev->doorbell_index.sdma_doorbell_range = 20;
 }
 
+static void nv_pre_asic_init(struct amdgpu_device *adev)
+{
+}
+
 static const struct amdgpu_asic_funcs nv_asic_funcs =
 {
        .read_disabled_bios = &nv_read_disabled_bios,
@@ -709,6 +680,7 @@ static const struct amdgpu_asic_funcs nv_asic_funcs =
        .need_reset_on_init = &nv_need_reset_on_init,
        .get_pcie_replay_count = &nv_get_pcie_replay_count,
        .supports_baco = &nv_asic_supports_baco,
+       .pre_asic_init = &nv_pre_asic_init,
 };
 
 static int nv_common_early_init(void *handle)