#define SPT_PMC_LTR_SCC 0x3A0
#define SPT_PMC_LTR_ISH 0x3A4
+#define SPT_PMC_ACPI_PM_TMR_CTL_OFFSET 0x18FC
+
/* Sunrise Point: PGD PFET Enable Ack Status Registers */
enum ppfear_regs {
SPT_PMC_XRAM_PPFEAR0A = 0x590,
#define SPT_PMC_VRIC1_SLPS0LVEN BIT(13)
#define SPT_PMC_VRIC1_XTALSDQDIS BIT(22)
+#define SPT_PMC_BIT_ACPI_PM_TMR_DISABLE BIT(1)
+
/* Cannonlake Power Management Controller register offsets */
#define CNP_PMC_SLPS0_DBG_OFFSET 0x10B4
#define CNP_PMC_PM_CFG_OFFSET 0x1818
const u8 *lpm_reg_index;
const u32 pson_residency_offset;
const u32 pson_residency_counter_step;
+ const u32 acpi_pm_tmr_ctl_offset;
+ const u32 acpi_pm_tmr_disable_bit;
};
/**
u32 die_c6_offset;
struct telem_endpoint *punit_ep;
struct pmc_info *regmap_list;
+
+ bool enable_acpi_pm_timer_on_resume;
};
enum pmc_index {