Merge tag 'bitmap-for-6.7' of https://github.com/norov/linux

[J-linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_vcn.h

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index a3eed90b6af090478142f3936323742774a7ddcb..514c98ea144f9558905ff01f16720b7f0c8b017d 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -33,7 +33,7 @@
 #define AMDGPU_VCN_MAX_ENC_RINGS       3
 
 #define AMDGPU_MAX_VCN_INSTANCES       4
-#define AMDGPU_MAX_VCN_ENC_RINGS  AMDGPU_VCN_MAX_ENC_RINGS * AMDGPU_MAX_VCN_INSTANCES
+#define AMDGPU_MAX_VCN_ENC_RINGS  (AMDGPU_VCN_MAX_ENC_RINGS * AMDGPU_MAX_VCN_INSTANCES)
 
 #define AMDGPU_VCN_HARVEST_VCN0 (1 << 0)
 #define AMDGPU_VCN_HARVEST_VCN1 (1 << 1)
@@ -169,6 +169,9 @@
 #define AMDGPU_VCN_SMU_VERSION_INFO_FLAG (1 << 11)
 #define AMDGPU_VCN_SMU_DPM_INTERFACE_FLAG (1 << 11)
 #define AMDGPU_VCN_VF_RB_SETUP_FLAG (1 << 14)
+#define AMDGPU_VCN_VF_RB_DECOUPLE_FLAG (1 << 15)
+
+#define MAX_NUM_VCN_RB_SETUP 4
 
 #define AMDGPU_VCN_IB_FLAG_DECODE_BUFFER       0x00000001
 #define AMDGPU_VCN_CMD_FLAG_MSG_BUFFER         0x00000001
@@ -335,15 +338,30 @@ struct amdgpu_fw_shared {
        struct amdgpu_fw_shared_smu_interface_info smu_interface_info;
 };
 
+struct amdgpu_vcn_rb_setup_info {
+       uint32_t  rb_addr_lo;
+       uint32_t  rb_addr_hi;
+       uint32_t  rb_size;
+};
+
 struct amdgpu_fw_shared_rb_setup {
        uint32_t is_rb_enabled_flags;
-       uint32_t rb_addr_lo;
-       uint32_t rb_addr_hi;
-       uint32_t  rb_size;
-       uint32_t  rb4_addr_lo;
-       uint32_t  rb4_addr_hi;
-       uint32_t  rb4_size;
-       uint32_t  reserved[6];
+
+       union {
+               struct {
+                       uint32_t rb_addr_lo;
+                       uint32_t rb_addr_hi;
+                       uint32_t  rb_size;
+                       uint32_t  rb4_addr_lo;
+                       uint32_t  rb4_addr_hi;
+                       uint32_t  rb4_size;
+                       uint32_t  reserved[6];
+               };
+
+               struct {
+                       struct amdgpu_vcn_rb_setup_info rb_info[MAX_NUM_VCN_RB_SETUP];
+               };
+       };
 };
 
 struct amdgpu_fw_shared_drm_key_wa {
@@ -351,6 +369,11 @@ struct amdgpu_fw_shared_drm_key_wa {
        uint8_t  reserved[3];
 };
 
+struct amdgpu_fw_shared_queue_decouple {
+       uint8_t  is_enabled;
+       uint8_t  reserved[7];
+};
+
 struct amdgpu_vcn4_fw_shared {
        uint32_t present_flag_0;
        uint8_t pad[12];
@@ -361,6 +384,8 @@ struct amdgpu_vcn4_fw_shared {
        struct amdgpu_fw_shared_rb_setup rb_setup;
        struct amdgpu_fw_shared_smu_interface_info smu_dpm_interface;
        struct amdgpu_fw_shared_drm_key_wa drm_key_wa;
+       uint8_t pad3[9];
+       struct amdgpu_fw_shared_queue_decouple decouple;
 };
 
 struct amdgpu_vcn_fwlog {
@@ -378,6 +403,15 @@ struct amdgpu_vcn_decode_buffer {
        uint32_t pad[30];
 };
 
+struct amdgpu_vcn_rb_metadata {
+       uint32_t size;
+       uint32_t present_flag_0;
+
+       uint8_t version;
+       uint8_t ring_id;
+       uint8_t pad[26];
+};
+
 #define VCN_BLOCK_ENCODE_DISABLE_MASK 0x80
 #define VCN_BLOCK_DECODE_DISABLE_MASK 0x40
 #define VCN_BLOCK_QUEUE_DISABLE_MASK 0xC0