Merge tag 'arm-defconfig-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

[J-linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu.h

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 7606e3b6361eaa18ce76b17dbc625845f5d18ba2..30ce6bb6fa77a42464c382c2d8d6774625fedf4b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -86,11 +86,13 @@
 #include "amdgpu_gmc.h"
 #include "amdgpu_gfx.h"
 #include "amdgpu_sdma.h"
+#include "amdgpu_lsdma.h"
 #include "amdgpu_nbio.h"
 #include "amdgpu_hdp.h"
 #include "amdgpu_dm.h"
 #include "amdgpu_virt.h"
 #include "amdgpu_csa.h"
+#include "amdgpu_mes_ctx.h"
 #include "amdgpu_gart.h"
 #include "amdgpu_debugfs.h"
 #include "amdgpu_job.h"
@@ -179,7 +181,7 @@ extern int amdgpu_sched_jobs;
 extern int amdgpu_sched_hw_submission;
 extern uint amdgpu_pcie_gen_cap;
 extern uint amdgpu_pcie_lane_cap;
-extern uint amdgpu_cg_mask;
+extern u64 amdgpu_cg_mask;
 extern uint amdgpu_pg_mask;
 extern uint amdgpu_sdma_phase_quantum;
 extern char *amdgpu_disable_cu;
@@ -207,6 +209,7 @@ extern int amdgpu_async_gfx_ring;
 extern int amdgpu_mcbp;
 extern int amdgpu_discovery;
 extern int amdgpu_mes;
+extern int amdgpu_mes_kiq;
 extern int amdgpu_noretry;
 extern int amdgpu_force_asic_type;
 extern int amdgpu_smartshift_bias;
@@ -322,7 +325,7 @@ int amdgpu_device_ip_set_powergating_state(void *dev,
                                           enum amd_ip_block_type block_type,
                                           enum amd_powergating_state state);
 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
-                                           u32 *flags);
+                                           u64 *flags);
 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev,
                                   enum amd_ip_block_type block_type);
 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev,
@@ -641,6 +644,7 @@ enum amd_hw_ip_block_type {
        SDMA5_HWIP,
        SDMA6_HWIP,
        SDMA7_HWIP,
+       LSDMA_HWIP,
        MMHUB_HWIP,
        ATHUB_HWIP,
        NBIO_HWIP,
@@ -666,10 +670,13 @@ enum amd_hw_ip_block_type {
        MAX_HWIP
 };
 
-#define HWIP_MAX_INSTANCE      10
+#define HWIP_MAX_INSTANCE      11
 
 #define HW_ID_MAX              300
 #define IP_VERSION(mj, mn, rv) (((mj) << 16) | ((mn) << 8) | (rv))
+#define IP_VERSION_MAJ(ver) ((ver) >> 16)
+#define IP_VERSION_MIN(ver) (((ver) >> 8) & 0xFF)
+#define IP_VERSION_REV(ver) ((ver) & 0xFF)
 
 struct amd_powerplay {
        void *pp_handle;
@@ -717,6 +724,26 @@ struct ip_discovery_top;
                                          (rid == 0x01) || \
                                          (rid == 0x10))))
 
+struct amdgpu_mqd_prop {
+       uint64_t mqd_gpu_addr;
+       uint64_t hqd_base_gpu_addr;
+       uint64_t rptr_gpu_addr;
+       uint64_t wptr_gpu_addr;
+       uint32_t queue_size;
+       bool use_doorbell;
+       uint32_t doorbell_index;
+       uint64_t eop_gpu_addr;
+       uint32_t hqd_pipe_priority;
+       uint32_t hqd_queue_priority;
+       bool hqd_active;
+};
+
+struct amdgpu_mqd {
+       unsigned mqd_size;
+       int (*init_mqd)(struct amdgpu_device *adev, void *mqd,
+                       struct amdgpu_mqd_prop *p);
+};
+
 #define AMDGPU_RESET_MAGIC_NUM 64
 #define AMDGPU_MAX_DF_PERFMONS 4
 #define AMDGPU_PRODUCT_NAME_LEN 64
@@ -860,7 +887,7 @@ struct amdgpu_device {
        /* powerplay */
        struct amd_powerplay            powerplay;
        struct amdgpu_pm                pm;
-       u32                             cg_flags;
+       u64                             cg_flags;
        u32                             pg_flags;
 
        /* nbio */
@@ -884,6 +911,9 @@ struct amdgpu_device {
        /* sdma */
        struct amdgpu_sdma              sdma;
 
+       /* lsdma */
+       struct amdgpu_lsdma             lsdma;
+
        /* uvd */
        struct amdgpu_uvd               uvd;
 
@@ -916,7 +946,9 @@ struct amdgpu_device {
 
        /* mes */
        bool                            enable_mes;
+       bool                            enable_mes_kiq;
        struct amdgpu_mes               mes;
+       struct amdgpu_mqd               mqds[AMDGPU_HW_IP_NUM];
 
        /* df */
        struct amdgpu_df                df;
@@ -978,10 +1010,10 @@ struct amdgpu_device {
        bool                            runpm;
        bool                            in_runpm;
        bool                            has_pr3;
-       bool                            is_fw_fb;
 
        bool                            pm_sysfs_en;
        bool                            ucode_sysfs_en;
+       bool                            psp_sysfs_en;
 
        /* Chip product information */
        char                            product_number[16];
@@ -1013,6 +1045,9 @@ struct amdgpu_device {
        /* reset dump register */
        uint32_t                        *reset_dump_reg_list;
        int                             num_regs;
+
+       bool                            scpm_enabled;
+       uint32_t                        scpm_status;
 };
 
 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
@@ -1185,7 +1220,8 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
 #define amdgpu_asic_flush_hdp(adev, r) \
        ((adev)->asic_funcs->flush_hdp ? (adev)->asic_funcs->flush_hdp((adev), (r)) : (adev)->hdp.funcs->flush_hdp((adev), (r)))
 #define amdgpu_asic_invalidate_hdp(adev, r) \
-       ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : (adev)->hdp.funcs->invalidate_hdp((adev), (r)))
+       ((adev)->asic_funcs->invalidate_hdp ? (adev)->asic_funcs->invalidate_hdp((adev), (r)) : \
+        ((adev)->hdp.funcs->invalidate_hdp ? (adev)->hdp.funcs->invalidate_hdp((adev), (r)) : 0))
 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev))
 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1)))