Merge tag 'nfsd-5.19-3' of git://git.kernel.org/pub/scm/linux/kernel/git/cel/linux

[J-linux.git] / drivers / gpu / drm / amd / amdgpu / gfx_v10_0.c

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 65a4126135b0e23c540166d4652b3b1fa144791d..c5f46d264b23d6887baa1ac6d86f8a90ca479826 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -5111,7 +5111,7 @@ static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
        mutex_unlock(&adev->srbm_mutex);
 
        /* Initialize all compute VMIDs to have no GDS, GWS, or OA
-          acccess. These should be enabled by FW for target VMIDs. */
+          access. These should be enabled by FW for target VMIDs. */
        for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
                WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
                WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
@@ -6898,7 +6898,7 @@ static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
        tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
                            (order_base_2(prop->queue_size / 4) - 1));
        tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
-                           ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
+                           (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
 #ifdef __BIG_ENDIAN
        tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
 #endif
@@ -6919,23 +6919,6 @@ static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
        mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
        mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
 
-       tmp = 0;
-       /* enable the doorbell if requested */
-       if (prop->use_doorbell) {
-               tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
-               tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
-                               DOORBELL_OFFSET, prop->doorbell_index);
-
-               tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
-                                   DOORBELL_EN, 1);
-               tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
-                                   DOORBELL_SOURCE, 0);
-               tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
-                                   DOORBELL_HIT, 0);
-       }
-
-       mqd->cp_hqd_pq_doorbell_control = tmp;
-
        /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
        mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
 
@@ -6973,20 +6956,6 @@ static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
        /* disable wptr polling */
        WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
 
-       /* write the EOP addr */
-       WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
-              mqd->cp_hqd_eop_base_addr_lo);
-       WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
-              mqd->cp_hqd_eop_base_addr_hi);
-
-       /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
-       WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
-              mqd->cp_hqd_eop_control);
-
-       /* enable doorbell? */
-       WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
-              mqd->cp_hqd_pq_doorbell_control);
-
        /* disable the queue if it's active */
        if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
                WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
@@ -7005,6 +6974,19 @@ static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
                       mqd->cp_hqd_pq_wptr_hi);
        }
 
+       /* disable doorbells */
+       WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
+
+       /* write the EOP addr */
+       WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
+              mqd->cp_hqd_eop_base_addr_lo);
+       WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
+              mqd->cp_hqd_eop_base_addr_hi);
+
+       /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
+       WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
+              mqd->cp_hqd_eop_control);
+
        /* set the pointer to the MQD */
        WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
               mqd->cp_mqd_base_addr_lo);