Merge patch "Enable SPCR table for console output on RISC-V"

[J-linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_jpeg.h

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
index aea31d61d991b8f56c3610a889023d3c6f3e441e..f9cdd873ac9b026e448fe4ae3510360669189930 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h
@@ -60,6 +60,37 @@
                RREG32_SOC15(JPEG, inst_idx, mmUVD_DPG_LMA_DATA);                               \
        })
 
+#define WREG32_SOC24_JPEG_DPG_MODE(inst_idx, offset, value, indirect)          \
+       do {                                                                    \
+               WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx),                    \
+                            regUVD_DPG_LMA_DATA, value);                       \
+               WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx),                    \
+                            regUVD_DPG_LMA_MASK, 0xFFFFFFFF);                  \
+               WREG32_SOC15(                                                   \
+                       JPEG, GET_INST(JPEG, inst_idx),                         \
+                       regUVD_DPG_LMA_CTL,                                     \
+                       (UVD_DPG_LMA_CTL__READ_WRITE_MASK |                     \
+                        offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT |    \
+                        indirect << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT));        \
+       } while (0)
+
+#define RREG32_SOC24_JPEG_DPG_MODE(inst_idx, offset, mask_en)                  \
+       do {                                                                    \
+               WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx),                    \
+                       regUVD_DPG_LMA_MASK, 0xFFFFFFFF);                       \
+               WREG32_SOC15(JPEG, GET_INST(JPEG, inst_idx),                    \
+                       regUVD_DPG_LMA_CTL,                                     \
+                       (UVD_DPG_LMA_CTL__MASK_EN_MASK |                        \
+                       offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT));    \
+               RREG32_SOC15(JPEG, inst_idx, regUVD_DPG_LMA_DATA);              \
+       } while (0)
+
+#define ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, offset, value, indirect)          \
+       do {                                                                    \
+               *adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = offset;       \
+               *adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = value;        \
+       } while (0)
+
 struct amdgpu_jpeg_reg{
        unsigned jpeg_pitch[AMDGPU_MAX_JPEG_RINGS];
 };