Merge branch 'asoc-5.3' into asoc-5.4

[J-linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_ucode.h

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
index 9b096228a02f93327e7a29260eee7c91f83b38e8..c1fb6dc86440d880593e9554d301dbacffe5274c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
@@ -23,6 +23,8 @@
 #ifndef __AMDGPU_UCODE_H__
 #define __AMDGPU_UCODE_H__
 
+#include "amdgpu_socbb.h"
+
 struct common_firmware_header {
        uint32_t size_bytes; /* size of the entire header+image(s) in bytes */
        uint32_t header_size_bytes; /* size of just the header in bytes */
@@ -56,6 +58,19 @@ struct smc_firmware_header_v2_0 {
        uint32_t ppt_size_bytes; /* soft pptable size */
 };
 
+struct smc_soft_pptable_entry {
+        uint32_t id;
+        uint32_t ppt_offset_bytes;
+        uint32_t ppt_size_bytes;
+};
+
+/* version_major=2, version_minor=1 */
+struct smc_firmware_header_v2_1 {
+        struct smc_firmware_header_v1_0 v1_0;
+        uint32_t pptable_count;
+        uint32_t pptable_entry_offset;
+};
+
 /* version_major=1, version_minor=0 */
 struct psp_firmware_header_v1_0 {
        struct common_firmware_header header;
@@ -70,6 +85,9 @@ struct psp_firmware_header_v1_1 {
        uint32_t toc_header_version;
        uint32_t toc_offset_bytes;
        uint32_t toc_size_bytes;
+       uint32_t kdb_header_version;
+       uint32_t kdb_offset_bytes;
+       uint32_t kdb_size_bytes;
 };
 
 /* version_major=1, version_minor=0 */
@@ -91,6 +109,21 @@ struct gfx_firmware_header_v1_0 {
        uint32_t jt_size;  /* size of jt */
 };
 
+/* version_major=1, version_minor=0 */
+struct mes_firmware_header_v1_0 {
+       struct common_firmware_header header;
+       uint32_t mes_ucode_version;
+       uint32_t mes_ucode_size_bytes;
+       uint32_t mes_ucode_offset_bytes;
+       uint32_t mes_ucode_data_version;
+       uint32_t mes_ucode_data_size_bytes;
+       uint32_t mes_ucode_data_offset_bytes;
+       uint32_t mes_uc_start_addr_lo;
+       uint32_t mes_uc_start_addr_hi;
+       uint32_t mes_data_start_addr_lo;
+       uint32_t mes_data_start_addr_hi;
+};
+
 /* version_major=1, version_minor=0 */
 struct rlc_firmware_header_v1_0 {
        struct common_firmware_header header;
@@ -182,6 +215,13 @@ struct gpu_info_firmware_v1_1 {
        uint32_t num_packer_per_sc;
 };
 
+/* gpu info payload
+ * version_major=1, version_minor=1 */
+struct gpu_info_firmware_v1_2 {
+       struct gpu_info_firmware_v1_1 v1_1;
+       struct gpu_info_soc_bounding_box_v1_0 soc_bounding_box;
+};
+
 /* version_major=1, version_minor=0 */
 struct gpu_info_firmware_header_v1_0 {
        struct common_firmware_header header;
@@ -229,6 +269,8 @@ enum AMDGPU_UCODE_ID {
        AMDGPU_UCODE_ID_CP_MEC1_JT,
        AMDGPU_UCODE_ID_CP_MEC2,
        AMDGPU_UCODE_ID_CP_MEC2_JT,
+       AMDGPU_UCODE_ID_CP_MES,
+       AMDGPU_UCODE_ID_CP_MES_DATA,
        AMDGPU_UCODE_ID_RLC_G,
        AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL,
        AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM,
@@ -241,6 +283,8 @@ enum AMDGPU_UCODE_ID {
        AMDGPU_UCODE_ID_VCN,
        AMDGPU_UCODE_ID_DMCU_ERAM,
        AMDGPU_UCODE_ID_DMCU_INTV,
+       AMDGPU_UCODE_ID_VCN0_RAM,
+       AMDGPU_UCODE_ID_VCN1_RAM,
        AMDGPU_UCODE_ID_MAXIMUM,
 };