Merge tag '6.13-rc-part1-SMB3-client-fixes' of git://git.samba.org/sfrench/cifs-2.6

[J-linux.git] / drivers / gpu / drm / amd / amdgpu / sdma_v6_0.c

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
index 208a1fa9d4e7f2ea3ca3548e359f5f1e1cb886b1..d46128b0ec9202fdcd27f9423826406b3c49b261 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
@@ -469,14 +469,16 @@ static void sdma_v6_0_enable(struct amdgpu_device *adev, bool enable)
 }
 
 /**
 }
 
 /**

- * sdma_v6_0_gfx_resume - setup and start the async dma engines
+ * sdma_v6_0_gfx_resume_instance - start/restart a certain sdma engine

  *
  * @adev: amdgpu_device pointer
  *
  * @adev: amdgpu_device pointer

+ * @i: instance
+ * @restore: used to restore wptr when restart

  *
  *

- * Set up the gfx DMA ring buffers and enable them.
- * Returns 0 for success, error for failure.
+ * Set up the gfx DMA ring buffers and enable them. On restart, we will restore wptr and rptr.
+ * Return 0 for success.

  */
  */

-static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev)
+static int sdma_v6_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool restore)

 {
        struct amdgpu_ring *ring;
        u32 rb_cntl, ib_cntl;
 {
        struct amdgpu_ring *ring;
        u32 rb_cntl, ib_cntl;


@@ -485,132 +487,152 @@ static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev)
        u32 doorbell_offset;
        u32 temp;
        u64 wptr_gpu_addr;
        u32 doorbell_offset;
        u32 temp;
        u64 wptr_gpu_addr;

-       int i, r;
-
-       for (i = 0; i < adev->sdma.num_instances; i++) {
-               ring = &adev->sdma.instance[i].ring;

 
 

-               if (!amdgpu_sriov_vf(adev))
-                       WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
+       ring = &adev->sdma.instance[i].ring;
+       if (!amdgpu_sriov_vf(adev))
+               WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);

 
 

-               /* Set ring buffer size in dwords */
-               rb_bufsz = order_base_2(ring->ring_size / 4);
-               rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));
-               rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz);
+       /* Set ring buffer size in dwords */
+       rb_bufsz = order_base_2(ring->ring_size / 4);
+       rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));
+       rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz);

 #ifdef __BIG_ENDIAN
 #ifdef __BIG_ENDIAN

-               rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1);
-               rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL,
-                                       RPTR_WRITEBACK_SWAP_ENABLE, 1);
+       rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1);
+       rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL,
+                               RPTR_WRITEBACK_SWAP_ENABLE, 1);

 #endif
 #endif

-               rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1);
-               WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
-
-               /* Initialize the ring buffer's read and write pointers */
+       rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1);
+       WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
+
+       /* Initialize the ring buffer's read and write pointers */
+       if (restore) {
+               WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), lower_32_bits(ring->wptr << 2));
+               WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), upper_32_bits(ring->wptr << 2));
+               WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr << 2));
+               WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
+       } else {

                WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0);
                WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0);
                WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0);
                WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0);
                WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0);
                WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0);
                WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0);
                WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0);

+       }
+       /* setup the wptr shadow polling */
+       wptr_gpu_addr = ring->wptr_gpu_addr;
+       WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO),
+              lower_32_bits(wptr_gpu_addr));
+       WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI),
+              upper_32_bits(wptr_gpu_addr));
+
+       /* set the wb address whether it's enabled or not */
+       WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI),
+              upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
+       WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO),
+              lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
+
+       rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
+       rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0);
+       rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, F32_WPTR_POLL_ENABLE, 1);
+
+       WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8);
+       WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40);
+
+       if (!restore)
+               ring->wptr = 0;

 
 

-               /* setup the wptr shadow polling */
-               wptr_gpu_addr = ring->wptr_gpu_addr;
-               WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO),
-                      lower_32_bits(wptr_gpu_addr));
-               WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI),
-                      upper_32_bits(wptr_gpu_addr));
-
-               /* set the wb address whether it's enabled or not */
-               WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI),
-                      upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
-               WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO),
-                      lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
-
-               rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
-               rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0);
-               rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, F32_WPTR_POLL_ENABLE, 1);
+       /* before programing wptr to a less value, need set minor_ptr_update first */
+       WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1);

 
 

-               WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8);
-               WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40);
+       if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
+               WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2);
+               WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
+       }

 
 

-               ring->wptr = 0;
+       doorbell = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL));
+       doorbell_offset = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET));

 
 

-               /* before programing wptr to a less value, need set minor_ptr_update first */
-               WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1);
+       if (ring->use_doorbell) {
+               doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);
+               doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_QUEUE0_DOORBELL_OFFSET,
+                               OFFSET, ring->doorbell_index);
+       } else {
+               doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0);
+       }
+       WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell);
+       WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_offset);

 
 

-               if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
-                       WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2);
-                       WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
-               }
+       if (i == 0)
+               adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
+                                             ring->doorbell_index,
+                                             adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances);

 
 

-               doorbell = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL));
-               doorbell_offset = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET));
+       if (amdgpu_sriov_vf(adev))
+               sdma_v6_0_ring_set_wptr(ring);
+
+       /* set minor_ptr_update to 0 after wptr programed */
+       WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0);
+
+       /* Set up sdma hang watchdog */
+       temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL));
+       /* 100ms per unit */
+       temp = REG_SET_FIELD(temp, SDMA0_WATCHDOG_CNTL, QUEUE_HANG_COUNT,
+                            max(adev->usec_timeout/100000, 1));
+       WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL), temp);
+
+       /* Set up RESP_MODE to non-copy addresses */
+       temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL));
+       temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
+       temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
+       WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp);
+
+       /* program default cache read and write policy */
+       temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE));
+       /* clean read policy and write policy bits */
+       temp &= 0xFF0FFF;
+       temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
+                (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
+                SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);
+       WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp);

 
 

-               if (ring->use_doorbell) {
-                       doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);
-                       doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_QUEUE0_DOORBELL_OFFSET,
-                                       OFFSET, ring->doorbell_index);
-               } else {
-                       doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0);
-               }
-               WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell);
-               WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_offset);
-
-               if (i == 0)
-                       adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
-                                                     ring->doorbell_index,
-                                                     adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances);
-
-               if (amdgpu_sriov_vf(adev))
-                       sdma_v6_0_ring_set_wptr(ring);
-
-               /* set minor_ptr_update to 0 after wptr programed */
-               WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0);
-
-               /* Set up sdma hang watchdog */
-               temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL));
-               /* 100ms per unit */
-               temp = REG_SET_FIELD(temp, SDMA0_WATCHDOG_CNTL, QUEUE_HANG_COUNT,
-                                    max(adev->usec_timeout/100000, 1));
-               WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL), temp);
-
-               /* Set up RESP_MODE to non-copy addresses */
-               temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL));
-               temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
-               temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
-               WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp);
-
-               /* program default cache read and write policy */
-               temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE));
-               /* clean read policy and write policy bits */
-               temp &= 0xFF0FFF;
-               temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
-                        (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
-                        SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);
-               WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp);
-
-               if (!amdgpu_sriov_vf(adev)) {
-                       /* unhalt engine */
-                       temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));
-                       temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
-                       temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, TH1_RESET, 0);
-                       WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), temp);
-               }
+       if (!amdgpu_sriov_vf(adev)) {
+               /* unhalt engine */
+               temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));
+               temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
+               temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, TH1_RESET, 0);
+               WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), temp);
+       }

 
 

-               /* enable DMA RB */
-               rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 1);
-               WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
+       /* enable DMA RB */
+       rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 1);
+       WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);

 
 

-               ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));
-               ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 1);
+       ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));
+       ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 1);

 #ifdef __BIG_ENDIAN
 #ifdef __BIG_ENDIAN

-               ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1);
+       ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1);

 #endif
 #endif

-               /* enable DMA IBs */
-               WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);
+       /* enable DMA IBs */
+       WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);
+
+       if (amdgpu_sriov_vf(adev))
+               sdma_v6_0_enable(adev, true);
+
+       return amdgpu_ring_test_helper(ring);
+}

 
 

-               if (amdgpu_sriov_vf(adev))
-                       sdma_v6_0_enable(adev, true);
+/**
+ * sdma_v6_0_gfx_resume - setup and start the async dma engines
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Set up the gfx DMA ring buffers and enable them.
+ * Returns 0 for success, error for failure.
+ */
+static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev)
+{
+       int i, r;

 
 

-               r = amdgpu_ring_test_helper(ring);
+       for (i = 0; i < adev->sdma.num_instances; i++) {
+               r = sdma_v6_0_gfx_resume_instance(adev, i, false);

                if (r)
                        return r;
        }
                if (r)
                        return r;
        }


@@ -733,9 +755,9 @@ static int sdma_v6_0_load_microcode(struct amdgpu_device *adev)
        return 0;
 }
 
        return 0;
 }
 

-static int sdma_v6_0_soft_reset(void *handle)
+static int sdma_v6_0_soft_reset(struct amdgpu_ip_block *ip_block)

 {
 {

-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;

        u32 tmp;
        int i;
 
        u32 tmp;
        int i;
 


@@ -769,9 +791,9 @@ static int sdma_v6_0_soft_reset(void *handle)
        return sdma_v6_0_start(adev);
 }
 
        return sdma_v6_0_start(adev);
 }
 

-static bool sdma_v6_0_check_soft_reset(void *handle)
+static bool sdma_v6_0_check_soft_reset(struct amdgpu_ip_block *ip_block)

 {
 {

-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;

        struct amdgpu_ring *ring;
        int i, r;
        long tmo = msecs_to_jiffies(1000);
        struct amdgpu_ring *ring;
        int i, r;
        long tmo = msecs_to_jiffies(1000);


@@ -1272,9 +1294,9 @@ static void sdma_v6_0_set_ras_funcs(struct amdgpu_device *adev)
        }
 }
 
        }
 }
 

-static int sdma_v6_0_early_init(void *handle)
+static int sdma_v6_0_early_init(struct amdgpu_ip_block *ip_block)

 {
 {

-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;

        int r;
 
        r = amdgpu_sdma_init_microcode(adev, 0, true);
        int r;
 
        r = amdgpu_sdma_init_microcode(adev, 0, true);


@@ -1291,11 +1313,11 @@ static int sdma_v6_0_early_init(void *handle)
        return 0;
 }
 
        return 0;
 }
 

-static int sdma_v6_0_sw_init(void *handle)
+static int sdma_v6_0_sw_init(struct amdgpu_ip_block *ip_block)

 {
        struct amdgpu_ring *ring;
        int r, i;
 {
        struct amdgpu_ring *ring;
        int r, i;

-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;

        uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_6_0);
        uint32_t *ptr;
 
        uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_6_0);
        uint32_t *ptr;
 


@@ -1328,6 +1350,19 @@ static int sdma_v6_0_sw_init(void *handle)
                        return r;
        }
 
                        return r;
        }
 

+       adev->sdma.supported_reset =
+               amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring);
+       switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
+       case IP_VERSION(6, 0, 0):
+       case IP_VERSION(6, 0, 2):
+       case IP_VERSION(6, 0, 3):
+               if (adev->sdma.instance[0].fw_version >= 21)
+                       adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
+               break;
+       default:
+               break;
+       }
+

        if (amdgpu_sdma_ras_sw_init(adev)) {
                dev_err(adev->dev, "Failed to initialize sdma ras block!\n");
                return -EINVAL;
        if (amdgpu_sdma_ras_sw_init(adev)) {
                dev_err(adev->dev, "Failed to initialize sdma ras block!\n");
                return -EINVAL;


@@ -1340,17 +1375,22 @@ static int sdma_v6_0_sw_init(void *handle)
        else
                DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n");
 
        else
                DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n");
 

+       r = amdgpu_sdma_sysfs_reset_mask_init(adev);
+       if (r)
+               return r;
+

        return r;
 }
 
        return r;
 }
 

-static int sdma_v6_0_sw_fini(void *handle)
+static int sdma_v6_0_sw_fini(struct amdgpu_ip_block *ip_block)

 {
 {

-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;

        int i;
 
        for (i = 0; i < adev->sdma.num_instances; i++)
                amdgpu_ring_fini(&adev->sdma.instance[i].ring);
 
        int i;
 
        for (i = 0; i < adev->sdma.num_instances; i++)
                amdgpu_ring_fini(&adev->sdma.instance[i].ring);
 

+       amdgpu_sdma_sysfs_reset_mask_fini(adev);

        amdgpu_sdma_destroy_inst_ctx(adev, true);
 
        kfree(adev->sdma.ip_dump);
        amdgpu_sdma_destroy_inst_ctx(adev, true);
 
        kfree(adev->sdma.ip_dump);


@@ -1358,16 +1398,16 @@ static int sdma_v6_0_sw_fini(void *handle)
        return 0;
 }
 
        return 0;
 }
 

-static int sdma_v6_0_hw_init(void *handle)
+static int sdma_v6_0_hw_init(struct amdgpu_ip_block *ip_block)

 {
 {

-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;

 
        return sdma_v6_0_start(adev);
 }
 
 
        return sdma_v6_0_start(adev);
 }
 

-static int sdma_v6_0_hw_fini(void *handle)
+static int sdma_v6_0_hw_fini(struct amdgpu_ip_block *ip_block)

 {
 {

-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;

 
        if (amdgpu_sriov_vf(adev))
                return 0;
 
        if (amdgpu_sriov_vf(adev))
                return 0;


@@ -1378,18 +1418,14 @@ static int sdma_v6_0_hw_fini(void *handle)
        return 0;
 }
 
        return 0;
 }
 

-static int sdma_v6_0_suspend(void *handle)
+static int sdma_v6_0_suspend(struct amdgpu_ip_block *ip_block)

 {
 {

-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
-       return sdma_v6_0_hw_fini(adev);
+       return sdma_v6_0_hw_fini(ip_block);

 }
 
 }
 

-static int sdma_v6_0_resume(void *handle)
+static int sdma_v6_0_resume(struct amdgpu_ip_block *ip_block)

 {
 {

-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
-       return sdma_v6_0_hw_init(adev);
+       return sdma_v6_0_hw_init(ip_block);

 }
 
 static bool sdma_v6_0_is_idle(void *handle)
 }
 
 static bool sdma_v6_0_is_idle(void *handle)


@@ -1407,11 +1443,11 @@ static bool sdma_v6_0_is_idle(void *handle)
        return true;
 }
 
        return true;
 }
 

-static int sdma_v6_0_wait_for_idle(void *handle)
+static int sdma_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block)

 {
        unsigned i;
        u32 sdma0, sdma1;
 {
        unsigned i;
        u32 sdma0, sdma1;

-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;

 
        for (i = 0; i < adev->usec_timeout; i++) {
                sdma0 = RREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG));
 
        for (i = 0; i < adev->usec_timeout; i++) {
                sdma0 = RREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG));


@@ -1469,6 +1505,31 @@ static int sdma_v6_0_ring_preempt_ib(struct amdgpu_ring *ring)
        return r;
 }
 
        return r;
 }
 

+static int sdma_v6_0_reset_queue(struct amdgpu_ring *ring, unsigned int vmid)
+{
+       struct amdgpu_device *adev = ring->adev;
+       int i, r;
+
+       if (amdgpu_sriov_vf(adev))
+               return -EINVAL;
+
+       for (i = 0; i < adev->sdma.num_instances; i++) {
+               if (ring == &adev->sdma.instance[i].ring)
+                       break;
+       }
+
+       if (i == adev->sdma.num_instances) {
+               DRM_ERROR("sdma instance not found\n");
+               return -EINVAL;
+       }
+
+       r = amdgpu_mes_reset_legacy_queue(adev, ring, vmid, true);
+       if (r)
+               return r;
+
+       return sdma_v6_0_gfx_resume_instance(adev, i, true);
+}
+

 static int sdma_v6_0_set_trap_irq_state(struct amdgpu_device *adev,
                                        struct amdgpu_irq_src *source,
                                        unsigned type,
 static int sdma_v6_0_set_trap_irq_state(struct amdgpu_device *adev,
                                        struct amdgpu_irq_src *source,
                                        unsigned type,


@@ -1556,9 +1617,9 @@ static void sdma_v6_0_get_clockgating_state(void *handle, u64 *flags)
 {
 }
 
 {
 }
 

-static void sdma_v6_0_print_ip_state(void *handle, struct drm_printer *p)
+static void sdma_v6_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)

 {
 {

-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;

        int i, j;
        uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_6_0);
        uint32_t instance_offset;
        int i, j;
        uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_6_0);
        uint32_t instance_offset;


@@ -1577,9 +1638,9 @@ static void sdma_v6_0_print_ip_state(void *handle, struct drm_printer *p)
        }
 }
 
        }
 }
 

-static void sdma_v6_0_dump_ip_state(void *handle)
+static void sdma_v6_0_dump_ip_state(struct amdgpu_ip_block *ip_block)

 {
 {

-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;

        int i, j;
        uint32_t instance_offset;
        uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_6_0);
        int i, j;
        uint32_t instance_offset;
        uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_6_0);


@@ -1601,7 +1662,6 @@ static void sdma_v6_0_dump_ip_state(void *handle)
 const struct amd_ip_funcs sdma_v6_0_ip_funcs = {
        .name = "sdma_v6_0",
        .early_init = sdma_v6_0_early_init,
 const struct amd_ip_funcs sdma_v6_0_ip_funcs = {
        .name = "sdma_v6_0",
        .early_init = sdma_v6_0_early_init,

-       .late_init = NULL,

        .sw_init = sdma_v6_0_sw_init,
        .sw_fini = sdma_v6_0_sw_fini,
        .hw_init = sdma_v6_0_hw_init,
        .sw_init = sdma_v6_0_sw_init,
        .sw_fini = sdma_v6_0_sw_fini,
        .hw_init = sdma_v6_0_hw_init,


@@ -1652,6 +1712,7 @@ static const struct amdgpu_ring_funcs sdma_v6_0_ring_funcs = {
        .emit_reg_write_reg_wait = sdma_v6_0_ring_emit_reg_write_reg_wait,
        .init_cond_exec = sdma_v6_0_ring_init_cond_exec,
        .preempt_ib = sdma_v6_0_ring_preempt_ib,
        .emit_reg_write_reg_wait = sdma_v6_0_ring_emit_reg_write_reg_wait,
        .init_cond_exec = sdma_v6_0_ring_init_cond_exec,
        .preempt_ib = sdma_v6_0_ring_preempt_ib,

+       .reset = sdma_v6_0_reset_queue,

 };
 
 static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev)
 };
 
 static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev)


@@ -1726,7 +1787,7 @@ static void sdma_v6_0_emit_fill_buffer(struct amdgpu_ib *ib,
                                       uint64_t dst_offset,
                                       uint32_t byte_count)
 {
                                       uint64_t dst_offset,
                                       uint32_t byte_count)
 {

-       ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_CONST_FILL);
+       ib->ptr[ib->length_dw++] = SDMA_PKT_CONSTANT_FILL_HEADER_OP(SDMA_OP_CONST_FILL);

        ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
        ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
        ib->ptr[ib->length_dw++] = src_data;
        ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
        ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
        ib->ptr[ib->length_dw++] = src_data;