Merge tag 'xtensa-20190715' of git://github.com/jcmvbkbc/linux-xtensa

[J-linux.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_virt.h

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
index 584947b7ccf3ce3b42749b793ffab42db59bb145..f5107731e9c4d2dc04ce8c5bebee1e7052f77d6e 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
@@ -48,6 +48,12 @@ struct amdgpu_vf_error_buffer {
        uint64_t data[AMDGPU_VF_ERROR_ENTRY_SIZE];
 };
 
+/* According to the fw feature, some new reg access modes are supported */
+#define AMDGPU_VIRT_REG_ACCESS_LEGACY          (1 << 0) /* directly mmio */
+#define AMDGPU_VIRT_REG_ACCESS_PSP_PRG_IH      (1 << 1) /* by PSP */
+#define AMDGPU_VIRT_REG_ACCESS_RLC             (1 << 2) /* by RLC */
+#define AMDGPU_VIRT_REG_SKIP_SEETING           (1 << 3) /* Skip setting reg */
+
 /**
  * struct amdgpu_virt_ops - amdgpu device virt operations
  */
@@ -59,6 +65,7 @@ struct amdgpu_virt_ops {
        void (*trans_msg)(struct amdgpu_device *adev, u32 req, u32 data1, u32 data2, u32 data3);
        int (*get_pp_clk)(struct amdgpu_device *adev, u32 type, char *buf);
        int (*force_dpm_level)(struct amdgpu_device *adev, u32 level);
+       void (*init_reg_access_mode)(struct amdgpu_device *adev);
 };
 
 /*
@@ -246,6 +253,7 @@ typedef struct amdgim_vf2pf_info_v2 amdgim_vf2pf_info ;
 struct amdgpu_virt {
        uint32_t                        caps;
        struct amdgpu_bo                *csa_obj;
+       void                            *csa_cpu_addr;
        bool chained_ib_support;
        uint32_t                        reg_val_offs;
        struct amdgpu_irq_src           ack_irq;
@@ -258,6 +266,7 @@ struct amdgpu_virt {
        uint32_t gim_feature;
        /* protect DPM events to GIM */
        struct mutex                    dpm_mutex;
+       uint32_t reg_access_mode;
 };
 
 #define amdgpu_sriov_enabled(adev) \
@@ -307,4 +316,9 @@ void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev);
 uint32_t amdgpu_virt_get_sclk(struct amdgpu_device *adev, bool lowest);
 uint32_t amdgpu_virt_get_mclk(struct amdgpu_device *adev, bool lowest);
 
+void amdgpu_virt_init_reg_access_mode(struct amdgpu_device *adev);
+bool amdgpu_virt_support_psp_prg_ih_reg(struct amdgpu_device *adev);
+bool amdgpu_virt_support_rlc_prg_reg(struct amdgpu_device *adev);
+bool amdgpu_virt_support_skip_setting(struct amdgpu_device *adev);
+
 #endif