arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2 /*
   3  * Copyright 2022 Toradex
   4  */
   5
   6 #include <dt-bindings/phy/phy-imx8-pcie.h>
   7 #include <dt-bindings/pwm/pwm.h>
   8 #include "imx8mp.dtsi"
   9
  10 / {
  11         chosen {
  12                 stdout-path = &uart3;
  13         };
  14
  15         aliases {
  16                 /* Ethernet aliases to ensure correct MAC addresses */
  17                 ethernet0 = &eqos;
  18                 ethernet1 = &fec;
  19                 rtc0 = &rtc_i2c;
  20                 rtc1 = &snvs_rtc;
  21         };
  22
  23         backlight: backlight {
  24                 compatible = "pwm-backlight";
  25                 brightness-levels = <0 45 63 88 119 158 203 255>;
  26                 default-brightness-level = <4>;
  27                 /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */
  28                 enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
  29                 pinctrl-names = "default";
  30                 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>;
  31                 power-supply = <&reg_3p3v>;
  32                 /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */
  33                 pwms = <&pwm3 0 6666667 PWM_POLARITY_INVERTED>;
  34                 status = "disabled";
  35         };
  36
  37         backlight_mezzanine: backlight-mezzanine {
  38                 compatible = "pwm-backlight";
  39                 brightness-levels = <0 45 63 88 119 158 203 255>;
  40                 default-brightness-level = <4>;
  41                 /* Verdin GPIO 4 (SODIMM 212) */
  42                 enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
  43                 /* Verdin PWM_2 (SODIMM 16) */
  44                 pwms = <&pwm2 0 6666667 PWM_POLARITY_INVERTED>;
  45                 status = "disabled";
  46         };
  47
  48         connector {
  49                 compatible = "gpio-usb-b-connector", "usb-b-connector";
  50                 id-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
  51                 label = "Type-C";
  52                 pinctrl-names = "default";
  53                 pinctrl-0 = <&pinctrl_usb_1_id>;
  54                 self-powered;
  55                 type = "micro";
  56                 vbus-supply = <&reg_usb1_vbus>;
  57
  58                 port {
  59                         usb_dr_connector: endpoint {
  60                                 remote-endpoint = <&usb3_dwc>;
  61                         };
  62                 };
  63         };
  64
  65         gpio-keys {
  66                 compatible = "gpio-keys";
  67                 pinctrl-names = "default";
  68                 pinctrl-0 = <&pinctrl_gpio_keys>;
  69
  70                 key-wakeup {
  71                         debounce-interval = <10>;
  72                         /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */
  73                         gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
  74                         label = "Wake-Up";
  75                         linux,code = <KEY_WAKEUP>;
  76                         wakeup-source;
  77                 };
  78         };
  79
  80         sound_hdmi: sound-hdmi {
  81                 compatible = "fsl,imx-audio-hdmi";
  82                 model = "audio-hdmi";
  83                 audio-cpu = <&aud2htx>;
  84                 hdmi-out;
  85                 status = "disabled";
  86         };
  87
  88         /* Carrier Board Supplies */
  89         reg_1p8v: regulator-1p8v {
  90                 compatible = "regulator-fixed";
  91                 regulator-max-microvolt = <1800000>;
  92                 regulator-min-microvolt = <1800000>;
  93                 regulator-name = "+V1.8_SW";
  94         };
  95
  96         reg_3p3v: regulator-3p3v {
  97                 compatible = "regulator-fixed";
  98                 regulator-max-microvolt = <3300000>;
  99                 regulator-min-microvolt = <3300000>;
 100                 regulator-name = "+V3.3_SW";
 101         };
 102
 103         reg_5p0v: regulator-5p0v {
 104                 compatible = "regulator-fixed";
 105                 regulator-max-microvolt = <5000000>;
 106                 regulator-min-microvolt = <5000000>;
 107                 regulator-name = "+V5_SW";
 108         };
 109
 110         /* Non PMIC On-module Supplies */
 111         reg_module_eth1phy: regulator-module-eth1phy {
 112                 compatible = "regulator-fixed";
 113                 enable-active-high;
 114                 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */
 115                 off-on-delay-us = <500000>;
 116                 pinctrl-names = "default";
 117                 pinctrl-0 = <&pinctrl_reg_eth>;
 118                 regulator-always-on;
 119                 regulator-boot-on;
 120                 regulator-max-microvolt = <3300000>;
 121                 regulator-min-microvolt = <3300000>;
 122                 regulator-name = "On-module +V3.3_ETH";
 123                 startup-delay-us = <200000>;
 124                 vin-supply = <&reg_vdd_3v3>;
 125         };
 126
 127         /*
 128          * By default we enable CTRL_SLEEP_MOCI#, this is required to have
 129          * peripherals on the carrier board powered.
 130          * If more granularity or power saving is required this can be disabled
 131          * in the carrier board device tree files.
 132          */
 133         reg_force_sleep_moci: regulator-force-sleep-moci {
 134                 compatible = "regulator-fixed";
 135                 enable-active-high;
 136                 /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
 137                 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>;
 138                 regulator-always-on;
 139                 regulator-boot-on;
 140                 regulator-name = "CTRL_SLEEP_MOCI#";
 141         };
 142
 143         reg_usb1_vbus: regulator-usb1-vbus {
 144                 compatible = "regulator-fixed";
 145                 enable-active-high;
 146                 /* Verdin USB_1_EN (SODIMM 155) */
 147                 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
 148                 pinctrl-names = "default";
 149                 pinctrl-0 = <&pinctrl_usb1_vbus>;
 150                 regulator-max-microvolt = <5000000>;
 151                 regulator-min-microvolt = <5000000>;
 152                 regulator-name = "USB_1_EN";
 153         };
 154
 155         reg_usb2_vbus: regulator-usb2-vbus {
 156                 compatible = "regulator-fixed";
 157                 enable-active-high;
 158                 /* Verdin USB_2_EN (SODIMM 185) */
 159                 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
 160                 pinctrl-names = "default";
 161                 pinctrl-0 = <&pinctrl_usb2_vbus>;
 162                 regulator-max-microvolt = <5000000>;
 163                 regulator-min-microvolt = <5000000>;
 164                 regulator-name = "USB_2_EN";
 165         };
 166
 167         reg_usdhc2_vmmc: regulator-usdhc2 {
 168                 compatible = "regulator-fixed";
 169                 enable-active-high;
 170                 /* Verdin SD_1_PWR_EN (SODIMM 76) */
 171                 gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>;
 172                 off-on-delay-us = <100000>;
 173                 pinctrl-names = "default";
 174                 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
 175                 regulator-max-microvolt = <3300000>;
 176                 regulator-min-microvolt = <3300000>;
 177                 regulator-name = "+V3.3_SD";
 178                 startup-delay-us = <2000>;
 179         };
 180
 181         reserved-memory {
 182                 #address-cells = <2>;
 183                 #size-cells = <2>;
 184                 ranges;
 185
 186                 /* Use the kernel configuration settings instead */
 187                 /delete-node/ linux,cma;
 188         };
 189 };
 190
 191 &A53_0 {
 192         cpu-supply = <&reg_vdd_arm>;
 193 };
 194
 195 &A53_1 {
 196         cpu-supply = <&reg_vdd_arm>;
 197 };
 198
 199 &A53_2 {
 200         cpu-supply = <&reg_vdd_arm>;
 201 };
 202
 203 &A53_3 {
 204         cpu-supply = <&reg_vdd_arm>;
 205 };
 206
 207 &cpu_alert0 {
 208         temperature = <95000>;
 209 };
 210
 211 &cpu_crit0 {
 212         temperature = <105000>;
 213 };
 214
 215 /* Verdin SPI_1 */
 216 &ecspi1 {
 217         #address-cells = <1>;
 218         #size-cells = <0>;
 219         cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
 220         pinctrl-names = "default";
 221         pinctrl-0 = <&pinctrl_ecspi1>;
 222 };
 223
 224 /* Verdin ETH_1 (On-module PHY) */
 225 &eqos {
 226         phy-handle = <&ethphy0>;
 227         phy-mode = "rgmii-id";
 228         pinctrl-names = "default";
 229         pinctrl-0 = <&pinctrl_eqos>;
 230         snps,force_thresh_dma_mode;
 231         snps,mtl-rx-config = <&mtl_rx_setup>;
 232         snps,mtl-tx-config = <&mtl_tx_setup>;
 233
 234         mdio {
 235                 compatible = "snps,dwmac-mdio";
 236                 #address-cells = <1>;
 237                 #size-cells = <0>;
 238
 239                 ethphy0: ethernet-phy@7 {
 240                         compatible = "ethernet-phy-ieee802.3-c22";
 241                         eee-broken-100tx;
 242                         eee-broken-1000t;
 243                         interrupt-parent = <&gpio1>;
 244                         interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
 245                         micrel,led-mode = <0>;
 246                         reg = <7>;
 247                 };
 248         };
 249
 250         mtl_rx_setup: rx-queues-config {
 251                 snps,rx-queues-to-use = <5>;
 252
 253                 queue0 {
 254                         snps,dcb-algorithm;
 255                         snps,priority = <0x1>;
 256                         snps,map-to-dma-channel = <0>;
 257                 };
 258
 259                 queue1 {
 260                         snps,dcb-algorithm;
 261                         snps,priority = <0x2>;
 262                         snps,map-to-dma-channel = <1>;
 263                 };
 264
 265                 queue2 {
 266                         snps,dcb-algorithm;
 267                         snps,priority = <0x4>;
 268                         snps,map-to-dma-channel = <2>;
 269                 };
 270
 271                 queue3 {
 272                         snps,dcb-algorithm;
 273                         snps,priority = <0x8>;
 274                         snps,map-to-dma-channel = <3>;
 275                 };
 276
 277                 queue4 {
 278                         snps,dcb-algorithm;
 279                         snps,priority = <0xf0>;
 280                         snps,map-to-dma-channel = <4>;
 281                 };
 282         };
 283
 284         mtl_tx_setup: tx-queues-config {
 285                 snps,tx-queues-to-use = <5>;
 286
 287                 queue0 {
 288                         snps,dcb-algorithm;
 289                         snps,priority = <0x1>;
 290                 };
 291
 292                 queue1 {
 293                         snps,dcb-algorithm;
 294                         snps,priority = <0x2>;
 295                 };
 296
 297                 queue2 {
 298                         snps,dcb-algorithm;
 299                         snps,priority = <0x4>;
 300                 };
 301
 302                 queue3 {
 303                         snps,dcb-algorithm;
 304                         snps,priority = <0x8>;
 305                 };
 306
 307                 queue4 {
 308                         snps,dcb-algorithm;
 309                         snps,priority = <0xf0>;
 310                 };
 311         };
 312 };
 313
 314 /* Verdin ETH_2_RGMII */
 315 &fec {
 316         fsl,magic-packet;
 317         phy-handle = <&ethphy1>;
 318         phy-mode = "rgmii-id";
 319         pinctrl-names = "default", "sleep";
 320         pinctrl-0 = <&pinctrl_fec>;
 321         pinctrl-1 = <&pinctrl_fec_sleep>;
 322
 323         verdin_eth2_mdio: mdio {
 324                 #address-cells = <1>;
 325                 #size-cells = <0>;
 326
 327                 ethphy1: ethernet-phy@7 {
 328                         compatible = "ethernet-phy-ieee802.3-c22";
 329                         interrupt-parent = <&gpio4>;
 330                         interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
 331                         micrel,led-mode = <0>;
 332                         reg = <7>;
 333                 };
 334         };
 335 };
 336
 337 /* Verdin CAN_1 */
 338 &flexcan1 {
 339         pinctrl-names = "default";
 340         pinctrl-0 = <&pinctrl_flexcan1>;
 341         status = "disabled";
 342 };
 343
 344 /* Verdin CAN_2 */
 345 &flexcan2 {
 346         pinctrl-names = "default";
 347         pinctrl-0 = <&pinctrl_flexcan2>;
 348         status = "disabled";
 349 };
 350
 351 /* Verdin QSPI_1 */
 352 &flexspi {
 353         pinctrl-names = "default";
 354         pinctrl-0 = <&pinctrl_flexspi0>;
 355 };
 356
 357 &gpio1 {
 358         gpio-line-names = "SODIMM_206",
 359                           "SODIMM_208",
 360                           "",
 361                           "",
 362                           "",
 363                           "SODIMM_210",
 364                           "SODIMM_212",
 365                           "SODIMM_216",
 366                           "SODIMM_218",
 367                           "",
 368                           "",
 369                           "SODIMM_16",
 370                           "SODIMM_155",
 371                           "SODIMM_157",
 372                           "SODIMM_185",
 373                           "SODIMM_91";
 374 };
 375
 376 &gpio2 {
 377         gpio-line-names = "",
 378                           "",
 379                           "",
 380                           "",
 381                           "",
 382                           "",
 383                           "SODIMM_143",
 384                           "SODIMM_141",
 385                           "",
 386                           "",
 387                           "SODIMM_161",
 388                           "",
 389                           "SODIMM_84",
 390                           "SODIMM_78",
 391                           "SODIMM_74",
 392                           "SODIMM_80",
 393                           "SODIMM_82",
 394                           "SODIMM_70",
 395                           "SODIMM_72";
 396 };
 397
 398 &gpio3 {
 399         gpio-line-names = "SODIMM_52",
 400                           "SODIMM_54",
 401                           "",
 402                           "",
 403                           "",
 404                           "",
 405                           "SODIMM_56",
 406                           "SODIMM_58",
 407                           "SODIMM_60",
 408                           "SODIMM_62",
 409                           "",
 410                           "",
 411                           "",
 412                           "",
 413                           "SODIMM_66",
 414                           "",
 415                           "SODIMM_64",
 416                           "",
 417                           "",
 418                           "SODIMM_34",
 419                           "SODIMM_19",
 420                           "",
 421                           "SODIMM_32",
 422                           "",
 423                           "",
 424                           "SODIMM_30",
 425                           "SODIMM_59",
 426                           "SODIMM_57",
 427                           "SODIMM_63",
 428                           "SODIMM_61";
 429 };
 430
 431 &gpio4 {
 432         gpio-line-names = "SODIMM_252",
 433                           "SODIMM_222",
 434                           "SODIMM_36",
 435                           "SODIMM_220",
 436                           "SODIMM_193",
 437                           "SODIMM_191",
 438                           "SODIMM_201",
 439                           "SODIMM_203",
 440                           "SODIMM_205",
 441                           "SODIMM_207",
 442                           "SODIMM_199",
 443                           "SODIMM_197",
 444                           "SODIMM_221",
 445                           "SODIMM_219",
 446                           "SODIMM_217",
 447                           "SODIMM_215",
 448                           "SODIMM_211",
 449                           "SODIMM_213",
 450                           "SODIMM_189",
 451                           "SODIMM_244",
 452                           "SODIMM_38",
 453                           "",
 454                           "SODIMM_76",
 455                           "SODIMM_135",
 456                           "SODIMM_133",
 457                           "SODIMM_17",
 458                           "SODIMM_24",
 459                           "SODIMM_26",
 460                           "SODIMM_21",
 461                           "SODIMM_256",
 462                           "SODIMM_48",
 463                           "SODIMM_44";
 464 };
 465
 466 /* Verdin HDMI_1 */
 467 &hdmi_tx {
 468         ddc-i2c-bus = <&i2c5>;
 469         pinctrl-names = "default";
 470         pinctrl-0 = <&pinctrl_hdmi>;
 471 };
 472
 473 /* On-module I2C */
 474 &i2c1 {
 475         clock-frequency = <400000>;
 476         pinctrl-names = "default", "gpio";
 477         pinctrl-0 = <&pinctrl_i2c1>;
 478         pinctrl-1 = <&pinctrl_i2c1_gpio>;
 479         scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 480         sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 481         single-master;
 482         status = "okay";
 483
 484         pca9450: pmic@25 {
 485                 compatible = "nxp,pca9450c";
 486                 interrupt-parent = <&gpio1>;
 487                 /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
 488                 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
 489                 pinctrl-names = "default";
 490                 pinctrl-0 = <&pinctrl_pmic>;
 491                 reg = <0x25>;
 492
 493                 /*
 494                  * The bootloader is expected to switch on LDO4 for the on-module +V3.3_ADC and the
 495                  * I2C level shifter for the TLA2024 ADC behind this PMIC.
 496                  */
 497
 498                 regulators {
 499                         BUCK1 {
 500                                 regulator-always-on;
 501                                 regulator-boot-on;
 502                                 regulator-max-microvolt = <1000000>;
 503                                 regulator-min-microvolt = <720000>;
 504                                 regulator-name = "On-module +VDD_SOC (BUCK1)";
 505                                 regulator-ramp-delay = <3125>;
 506                         };
 507
 508                         reg_vdd_arm: BUCK2 {
 509                                 nxp,dvs-run-voltage = <950000>;
 510                                 nxp,dvs-standby-voltage = <850000>;
 511                                 regulator-always-on;
 512                                 regulator-boot-on;
 513                                 regulator-max-microvolt = <1025000>;
 514                                 regulator-min-microvolt = <720000>;
 515                                 regulator-name = "On-module +VDD_ARM (BUCK2)";
 516                                 regulator-ramp-delay = <3125>;
 517                         };
 518
 519                         reg_vdd_3v3: BUCK4 {
 520                                 regulator-always-on;
 521                                 regulator-boot-on;
 522                                 regulator-max-microvolt = <3300000>;
 523                                 regulator-min-microvolt = <3300000>;
 524                                 regulator-name = "On-module +V3.3 (BUCK4)";
 525                         };
 526
 527                         reg_vdd_1v8: BUCK5 {
 528                                 regulator-always-on;
 529                                 regulator-boot-on;
 530                                 regulator-max-microvolt = <1800000>;
 531                                 regulator-min-microvolt = <1800000>;
 532                                 regulator-name = "PWR_1V8_MOCI (BUCK5)";
 533                         };
 534
 535                         BUCK6 {
 536                                 regulator-always-on;
 537                                 regulator-boot-on;
 538                                 regulator-max-microvolt = <1155000>;
 539                                 regulator-min-microvolt = <1045000>;
 540                                 regulator-name = "On-module +VDD_DDR (BUCK6)";
 541                         };
 542
 543                         LDO1 {
 544                                 regulator-always-on;
 545                                 regulator-boot-on;
 546                                 regulator-max-microvolt = <1950000>;
 547                                 regulator-min-microvolt = <1650000>;
 548                                 regulator-name = "On-module +V1.8_SNVS (LDO1)";
 549                         };
 550
 551                         LDO2 {
 552                                 regulator-always-on;
 553                                 regulator-boot-on;
 554                                 regulator-max-microvolt = <1150000>;
 555                                 regulator-min-microvolt = <800000>;
 556                                 regulator-name = "On-module +V0.8_SNVS (LDO2)";
 557                         };
 558
 559                         LDO3 {
 560                                 regulator-always-on;
 561                                 regulator-boot-on;
 562                                 regulator-max-microvolt = <1800000>;
 563                                 regulator-min-microvolt = <1800000>;
 564                                 regulator-name = "On-module +V1.8A (LDO3)";
 565                         };
 566
 567                         LDO4 {
 568                                 regulator-always-on;
 569                                 regulator-boot-on;
 570                                 regulator-max-microvolt = <3300000>;
 571                                 regulator-min-microvolt = <3300000>;
 572                                 regulator-name = "On-module +V3.3_ADC (LDO4)";
 573                         };
 574
 575                         reg_vdd_sdio: LDO5 {
 576                                 regulator-max-microvolt = <3300000>;
 577                                 regulator-min-microvolt = <1800000>;
 578                                 regulator-name = "On-module +V3.3_1.8_SD (LDO5)";
 579                         };
 580                 };
 581         };
 582
 583         rtc_i2c: rtc@32 {
 584                 compatible = "epson,rx8130";
 585                 reg = <0x32>;
 586         };
 587
 588         /* On-module temperature sensor */
 589         hwmon_temp_module: sensor@48 {
 590                 compatible = "ti,tmp1075";
 591                 reg = <0x48>;
 592                 vs-supply = <&reg_vdd_1v8>;
 593         };
 594
 595         verdin_som_adc: adc@49 {
 596                 compatible = "ti,ads1015";
 597                 reg = <0x49>;
 598                 #address-cells = <1>;
 599                 #size-cells = <0>;
 600                 #io-channel-cells = <1>;
 601
 602                 /* Verdin I2C_1 (ADC_4 - ADC_3) */
 603                 channel@0 {
 604                         reg = <0>;
 605                         ti,datarate = <4>;
 606                         ti,gain = <2>;
 607                 };
 608
 609                 /* Verdin I2C_1 (ADC_4 - ADC_1) */
 610                 channel@1 {
 611                         reg = <1>;
 612                         ti,datarate = <4>;
 613                         ti,gain = <2>;
 614                 };
 615
 616                 /* Verdin I2C_1 (ADC_3 - ADC_1) */
 617                 channel@2 {
 618                         reg = <2>;
 619                         ti,datarate = <4>;
 620                         ti,gain = <2>;
 621                 };
 622
 623                 /* Verdin I2C_1 (ADC_2 - ADC_1) */
 624                 channel@3 {
 625                         reg = <3>;
 626                         ti,datarate = <4>;
 627                         ti,gain = <2>;
 628                 };
 629
 630                 /* Verdin I2C_1 ADC_4 */
 631                 channel@4 {
 632                         reg = <4>;
 633                         ti,datarate = <4>;
 634                         ti,gain = <2>;
 635                 };
 636
 637                 /* Verdin I2C_1 ADC_3 */
 638                 channel@5 {
 639                         reg = <5>;
 640                         ti,datarate = <4>;
 641                         ti,gain = <2>;
 642                 };
 643
 644                 /* Verdin I2C_1 ADC_2 */
 645                 channel@6 {
 646                         reg = <6>;
 647                         ti,datarate = <4>;
 648                         ti,gain = <2>;
 649                 };
 650
 651                 /* Verdin I2C_1 ADC_1 */
 652                 channel@7 {
 653                         reg = <7>;
 654                         ti,datarate = <4>;
 655                         ti,gain = <2>;
 656                 };
 657         };
 658
 659         eeprom@50 {
 660                 compatible = "st,24c02";
 661                 pagesize = <16>;
 662                 reg = <0x50>;
 663         };
 664 };
 665
 666 /* Verdin I2C_2_DSI */
 667 &i2c2 {
 668         clock-frequency = <400000>;
 669         pinctrl-names = "default", "gpio";
 670         pinctrl-0 = <&pinctrl_i2c2>;
 671         pinctrl-1 = <&pinctrl_i2c2_gpio>;
 672         scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 673         sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 674         single-master;
 675
 676         atmel_mxt_ts_mezzanine: touch-mezzanine@4a {
 677                 compatible = "atmel,maxtouch";
 678                 /* Verdin GPIO_3 (SODIMM 210) */
 679                 interrupt-parent = <&gpio1>;
 680                 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
 681                 reg = <0x4a>;
 682                 /* Verdin GPIO_2 (SODIMM 208) */
 683                 reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
 684                 status = "disabled";
 685         };
 686 };
 687
 688 /* Verdin I2C_4_CSI */
 689 &i2c3 {
 690         clock-frequency = <400000>;
 691         pinctrl-names = "default", "gpio";
 692         pinctrl-0 = <&pinctrl_i2c3>;
 693         pinctrl-1 = <&pinctrl_i2c3_gpio>;
 694         scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 695         sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 696         single-master;
 697 };
 698
 699 /* Verdin I2C_1 */
 700 &i2c4 {
 701         clock-frequency = <400000>;
 702         pinctrl-names = "default", "gpio";
 703         pinctrl-0 = <&pinctrl_i2c4>;
 704         pinctrl-1 = <&pinctrl_i2c4_gpio>;
 705         scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 706         sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 707         single-master;
 708
 709         gpio_expander_21: gpio-expander@21 {
 710                 compatible = "nxp,pcal6416";
 711                 #gpio-cells = <2>;
 712                 gpio-controller;
 713                 reg = <0x21>;
 714                 vcc-supply = <&reg_3p3v>;
 715                 status = "disabled";
 716         };
 717
 718         lvds_ti_sn65dsi84: bridge@2c {
 719                 compatible = "ti,sn65dsi84";
 720                 /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */
 721                 /* Verdin GPIO_10_DSI (SODIMM 21) */
 722                 enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
 723                 pinctrl-names = "default";
 724                 pinctrl-0 = <&pinctrl_gpio_10_dsi>;
 725                 reg = <0x2c>;
 726                 status = "disabled";
 727         };
 728
 729         /* Current measurement into module VCC */
 730         hwmon: hwmon@40 {
 731                 compatible = "ti,ina219";
 732                 reg = <0x40>;
 733                 shunt-resistor = <10000>;
 734                 status = "disabled";
 735         };
 736
 737         hdmi_lontium_lt8912: hdmi@48 {
 738                 compatible = "lontium,lt8912b";
 739                 pinctrl-names = "default";
 740                 pinctrl-0 = <&pinctrl_gpio_10_dsi>, <&pinctrl_pwm_3_dsi_hpd_gpio>;
 741                 reg = <0x48>;
 742                 /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */
 743                 /* Verdin GPIO_10_DSI (SODIMM 21) */
 744                 reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
 745                 status = "disabled";
 746         };
 747
 748         atmel_mxt_ts: touch@4a {
 749                 compatible = "atmel,maxtouch";
 750                 /*
 751                  * Verdin GPIO_9_DSI
 752                  * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI84 IRQ albeit currently unused)
 753                  */
 754                 interrupt-parent = <&gpio4>;
 755                 interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
 756                 pinctrl-names = "default";
 757                 pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>;
 758                 reg = <0x4a>;
 759                 /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */
 760                 reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
 761                 status = "disabled";
 762         };
 763
 764         /* Temperature sensor on carrier board */
 765         hwmon_temp: sensor@4f {
 766                 compatible = "ti,tmp75c";
 767                 reg = <0x4f>;
 768                 status = "disabled";
 769         };
 770
 771         /* EEPROM on display adapter (MIPI DSI Display Adapter) */
 772         eeprom_display_adapter: eeprom@50 {
 773                 compatible = "st,24c02";
 774                 pagesize = <16>;
 775                 reg = <0x50>;
 776                 status = "disabled";
 777         };
 778
 779         /* EEPROM on carrier board */
 780         eeprom_carrier_board: eeprom@57 {
 781                 compatible = "st,24c02";
 782                 pagesize = <16>;
 783                 reg = <0x57>;
 784                 status = "disabled";
 785         };
 786 };
 787
 788 /* Verdin I2C_3_HDMI */
 789 &i2c5 {
 790         clock-frequency = <100000>;
 791         pinctrl-names = "default", "gpio";
 792         pinctrl-0 = <&pinctrl_i2c5>;
 793         pinctrl-1 = <&pinctrl_i2c5_gpio>;
 794         scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 795         sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 796         single-master;
 797 };
 798
 799 /* Verdin PCIE_1 */
 800 &pcie {
 801         pinctrl-names = "default";
 802         pinctrl-0 = <&pinctrl_pcie>;
 803         /* PCIE_1_RESET# (SODIMM 244) */
 804         reset-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>;
 805 };
 806
 807 &pcie_phy {
 808         clocks = <&hsio_blk_ctrl>;
 809         clock-names = "ref";
 810         fsl,clkreq-unsupported;
 811         fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
 812 };
 813
 814 /* Verdin PWM_1 */
 815 &pwm1 {
 816         pinctrl-names = "default";
 817         pinctrl-0 = <&pinctrl_pwm_1>;
 818         #pwm-cells = <3>;
 819 };
 820
 821 /* Verdin PWM_2 */
 822 &pwm2 {
 823         pinctrl-names = "default";
 824         pinctrl-0 = <&pinctrl_pwm_2>;
 825         #pwm-cells = <3>;
 826 };
 827
 828 /* Verdin PWM_3_DSI */
 829 &pwm3 {
 830         pinctrl-names = "default";
 831         pinctrl-0 = <&pinctrl_pwm_3>;
 832         #pwm-cells = <3>;
 833 };
 834
 835 /* TODO: Verdin I2S_1 */
 836
 837 /* TODO: Verdin I2S_2 */
 838
 839 &snvs_pwrkey {
 840         status = "okay";
 841 };
 842
 843 /* Verdin UART_1 */
 844 &uart1 {
 845         pinctrl-names = "default";
 846         pinctrl-0 = <&pinctrl_uart1>;
 847         uart-has-rtscts;
 848 };
 849
 850 /* Verdin UART_2 */
 851 &uart2 {
 852         pinctrl-names = "default";
 853         pinctrl-0 = <&pinctrl_uart2>;
 854         uart-has-rtscts;
 855 };
 856
 857 /* Verdin UART_3, used as the Linux Console */
 858 &uart3 {
 859         pinctrl-names = "default";
 860         pinctrl-0 = <&pinctrl_uart3>;
 861 };
 862
 863 /* Verdin UART_4, used for Bluetooth on Wi-Fi/Bluetooth SKUs */
 864 &uart4 {
 865         pinctrl-names = "default";
 866         pinctrl-0 = <&pinctrl_uart4>;
 867 };
 868
 869 /* Verdin USB_1 */
 870 &usb3_0 {
 871         fsl,disable-port-power-control;
 872         fsl,over-current-active-low;
 873         pinctrl-names = "default";
 874         pinctrl-0 = <&pinctrl_usb_1_oc_n>;
 875 };
 876
 877 &usb_dwc3_0 {
 878         /* dual role only, not full featured OTG */
 879         adp-disable;
 880         dr_mode = "otg";
 881         hnp-disable;
 882         maximum-speed = "high-speed";
 883         role-switch-default-mode = "peripheral";
 884         srp-disable;
 885         usb-role-switch;
 886
 887         port {
 888                 usb3_dwc: endpoint {
 889                         remote-endpoint = <&usb_dr_connector>;
 890                 };
 891         };
 892 };
 893
 894 /* Verdin USB_2 */
 895 &usb3_1 {
 896         fsl,disable-port-power-control;
 897 };
 898
 899 &usb3_phy1 {
 900         vbus-supply = <&reg_usb2_vbus>;
 901 };
 902
 903 &usb_dwc3_1 {
 904         dr_mode = "host";
 905 };
 906
 907 /* Verdin SD_1 */
 908 &usdhc2 {
 909         assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
 910         assigned-clock-rates = <400000000>;
 911         bus-width = <4>;
 912         cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 913         disable-wp;
 914         pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
 915         pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
 916         pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
 917         pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
 918         pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>;
 919         vmmc-supply = <&reg_usdhc2_vmmc>;
 920         vqmmc-supply = <&reg_vdd_sdio>;
 921 };
 922
 923 /* On-module eMMC */
 924 &usdhc3 {
 925         assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>;
 926         assigned-clock-rates = <400000000>;
 927         bus-width = <8>;
 928         non-removable;
 929         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 930         pinctrl-0 = <&pinctrl_usdhc3>;
 931         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 932         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 933         status = "okay";
 934 };
 935
 936 &wdog1 {
 937         fsl,ext-reset-output;
 938         pinctrl-names = "default";
 939         pinctrl-0 = <&pinctrl_wdog>;
 940         status = "okay";
 941 };
 942
 943 &iomuxc {
 944         pinctrl_bt_uart: btuartgrp {
 945                 fsl,pins =
 946                         <MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS        0x1c4>,
 947                         <MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX         0x1c4>,
 948                         <MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX         0x1c4>,
 949                         <MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS         0x1c4>;
 950         };
 951
 952         pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {
 953                 fsl,pins =
 954                         <MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29              0x1c4>; /* SODIMM 256 */
 955         };
 956
 957         pinctrl_ecspi1: ecspi1grp {
 958                 fsl,pins =
 959                         <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO          0x1c4>, /* SODIMM 198 */
 960                         <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI          0x4>,   /* SODIMM 200 */
 961                         <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK          0x4>,   /* SODIMM 196 */
 962                         <MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09            0x1c4>; /* SODIMM 202 */
 963         };
 964
 965         /* Connection On Board PHY */
 966         pinctrl_eqos: eqosgrp {
 967                 fsl,pins =
 968                         <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC                            0x3>,
 969                         <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO                          0x3>,
 970                         <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0                      0x91>,
 971                         <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1                      0x91>,
 972                         <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2                      0x91>,
 973                         <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3                      0x91>,
 974                         <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK      0x91>,
 975                         <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL                0x91>,
 976                         <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0                      0x1f>,
 977                         <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1                      0x1f>,
 978                         <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2                      0x1f>,
 979                         <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3                      0x1f>,
 980                         <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL                0x1f>,
 981                         <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK      0x1f>;
 982         };
 983
 984         /* ETH_INT# shared with TPM_INT# (usually N/A) */
 985         pinctrl_eth_tpm_int: ethtpmintgrp {
 986                 fsl,pins =
 987                         <MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10            0x1c4>;
 988         };
 989
 990         /* Connection Carrier Board PHY ETH_2 */
 991         pinctrl_fec: fecgrp {
 992                 fsl,pins =
 993                         <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC              0x3>,   /* SODIMM 193 */
 994                         <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO             0x3>,   /* SODIMM 191 */
 995                         <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0        0x91>,  /* SODIMM 201 */
 996                         <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1        0x91>,  /* SODIMM 203 */
 997                         <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2        0x91>,  /* SODIMM 205 */
 998                         <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3        0x91>,  /* SODIMM 207 */
 999                         <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC         0x91>,  /* SODIMM 197 */
1000                         <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL     0x91>,  /* SODIMM 199 */
1001                         <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0        0x1f>,  /* SODIMM 221 */
1002                         <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1        0x1f>,  /* SODIMM 219 */
1003                         <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2        0x1f>,  /* SODIMM 217 */
1004                         <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3        0x1f>,  /* SODIMM 215 */
1005                         <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL     0x1f>,  /* SODIMM 211 */
1006                         <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC        0x1f>,  /* SODIMM 213 */
1007                         <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18             0x1c4>; /* SODIMM 189 */
1008         };
1009
1010         pinctrl_fec_sleep: fecsleepgrp {
1011                 fsl,pins =
1012                         <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC              0x3>,   /* SODIMM 193 */
1013                         <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO             0x3>,   /* SODIMM 191 */
1014                         <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0        0x91>,  /* SODIMM 201 */
1015                         <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1        0x91>,  /* SODIMM 203 */
1016                         <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2        0x91>,  /* SODIMM 205 */
1017                         <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3        0x91>,  /* SODIMM 207 */
1018                         <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC         0x91>,  /* SODIMM 197 */
1019                         <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL     0x91>,  /* SODIMM 199 */
1020                         <MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12             0x1f>,  /* SODIMM 221 */
1021                         <MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13             0x1f>,  /* SODIMM 219 */
1022                         <MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14             0x1f>,  /* SODIMM 217 */
1023                         <MX8MP_IOMUXC_SAI1_TXD3__GPIO4_IO15             0x1f>,  /* SODIMM 215 */
1024                         <MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16             0x1f>,  /* SODIMM 211 */
1025                         <MX8MP_IOMUXC_SAI1_TXD5__GPIO4_IO17             0x1f>,  /* SODIMM 213 */
1026                         <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18             0x184>; /* SODIMM 189 */
1027         };
1028
1029         pinctrl_flexcan1: flexcan1grp {
1030                 fsl,pins =
1031                         <MX8MP_IOMUXC_SPDIF_RX__CAN1_RX                 0x154>, /* SODIMM 22 */
1032                         <MX8MP_IOMUXC_SPDIF_TX__CAN1_TX                 0x154>; /* SODIMM 20 */
1033         };
1034
1035         pinctrl_flexcan2: flexcan2grp {
1036                 fsl,pins =
1037                         <MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX                0x154>, /* SODIMM 26 */
1038                         <MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX                0x154>; /* SODIMM 24 */
1039         };
1040
1041         pinctrl_flexspi0: flexspi0grp {
1042                 fsl,pins =
1043                         <MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK          0x1c2>, /* SODIMM 52 */
1044                         <MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B       0x82>,  /* SODIMM 54 */
1045                         <MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS           0x82>,  /* SODIMM 66 */
1046                         <MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00     0x82>,  /* SODIMM 56 */
1047                         <MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01     0x82>,  /* SODIMM 58 */
1048                         <MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02     0x82>,  /* SODIMM 60 */
1049                         <MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03     0x82>,  /* SODIMM 62 */
1050                         <MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16          0x82>;  /* SODIMM 64 */
1051         };
1052
1053         pinctrl_gpio1: gpio1grp {
1054                 fsl,pins =
1055                         <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00            0x184>; /* SODIMM 206 */
1056         };
1057
1058         pinctrl_gpio2: gpio2grp {
1059                 fsl,pins =
1060                         <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01            0x1c4>; /* SODIMM 208 */
1061         };
1062
1063         pinctrl_gpio3: gpio3grp {
1064                 fsl,pins =
1065                         <MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05            0x184>; /* SODIMM 210 */
1066         };
1067
1068         pinctrl_gpio4: gpio4grp {
1069                 fsl,pins =
1070                         <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06            0x184>; /* SODIMM 212 */
1071         };
1072
1073         pinctrl_gpio5: gpio5grp {
1074                 fsl,pins =
1075                         <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07            0x184>; /* SODIMM 216 */
1076         };
1077
1078         pinctrl_gpio6: gpio6grp {
1079                 fsl,pins =
1080                         <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08            0x184>; /* SODIMM 218 */
1081         };
1082
1083         pinctrl_gpio7: gpio7grp {
1084                 fsl,pins =
1085                         <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03             0x184>; /* SODIMM 220 */
1086         };
1087
1088         pinctrl_gpio8: gpio8grp {
1089                 fsl,pins =
1090                         <MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01              0x184>; /* SODIMM 222 */
1091         };
1092
1093         /* Verdin GPIO_9_DSI (pulled-up as active-low) */
1094         pinctrl_gpio_9_dsi: gpio9dsigrp {
1095                 fsl,pins =
1096                         <MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25              0x1c4>; /* SODIMM 17 */
1097         };
1098
1099         /* Verdin GPIO_10_DSI */
1100         pinctrl_gpio_10_dsi: gpio10dsigrp {
1101                 fsl,pins =
1102                         <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28             0x1c4>; /* SODIMM 21 */
1103         };
1104
1105         /* Non-wifi MSP usage only */
1106         pinctrl_gpio_hog1: gpiohog1grp {
1107                 fsl,pins =
1108                         <MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12           0x1c4>, /* SODIMM 116 */
1109                         <MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11           0x1c4>, /* SODIMM 152 */
1110                         <MX8MP_IOMUXC_ECSPI2_SCLK__GPIO5_IO10           0x1c4>, /* SODIMM 164 */
1111                         <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13            0x1c4>; /* SODIMM 128 */
1112         };
1113
1114         /* USB_2_OC# */
1115         pinctrl_gpio_hog2: gpiohog2grp {
1116                 fsl,pins =
1117                         <MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02             0x1c4>; /* SODIMM 187 */
1118         };
1119
1120         pinctrl_gpio_hog3: gpiohog3grp {
1121                 fsl,pins =
1122                         /* CSI_1_MCLK */
1123                         <MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15            0x1c4>; /* SODIMM 91 */
1124         };
1125
1126         /* Wifi usage only */
1127         pinctrl_gpio_hog4: gpiohog4grp {
1128                 fsl,pins =
1129                         <MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28             0x1c4>, /* SODIMM 151 */
1130                         <MX8MP_IOMUXC_UART4_TXD__GPIO5_IO29             0x1c4>; /* SODIMM 153 */
1131         };
1132
1133         pinctrl_gpio_keys: gpiokeysgrp {
1134                 fsl,pins =
1135                         <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00             0x1c4>; /* SODIMM 252 */
1136         };
1137
1138         pinctrl_hdmi: hdmigrp {
1139                 fsl,pins =
1140                         <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC        0x140>, /* SODIMM 63 */
1141                         <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD        0x180>; /* SODIMM 61 */
1142         };
1143
1144         /* On-module I2C */
1145         pinctrl_i2c1: i2c1grp {
1146                 fsl,pins =
1147                         <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL                0x400001c6>,    /* PMIC_I2C_SCL */
1148                         <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA                0x400001c6>;    /* PMIC_I2C_SDA */
1149         };
1150
1151         pinctrl_i2c1_gpio: i2c1gpiogrp {
1152                 fsl,pins =
1153                         <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14              0x400001c6>,    /* PMIC_I2C_SCL */
1154                         <MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15              0x400001c6>;    /* PMIC_I2C_SDA */
1155         };
1156
1157         /* Verdin I2C_2_DSI */
1158         pinctrl_i2c2: i2c2grp {
1159                 fsl,pins =
1160                         <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL                0x400001c6>,    /* SODIMM 55 */
1161                         <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA                0x400001c6>;    /* SODIMM 53 */
1162         };
1163
1164         pinctrl_i2c2_gpio: i2c2gpiogrp {
1165                 fsl,pins =
1166                         <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16              0x400001c6>,    /* SODIMM 55 */
1167                         <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17              0x400001c6>;    /* SODIMM 53 */
1168         };
1169
1170         /* Verdin I2C_4_CSI */
1171         pinctrl_i2c3: i2c3grp {
1172                 fsl,pins =
1173                         <MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL                0x400001c6>,    /* SODIMM 95 */
1174                         <MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA                0x400001c6>;    /* SODIMM 93 */
1175         };
1176
1177         pinctrl_i2c3_gpio: i2c3gpiogrp {
1178                 fsl,pins =
1179                         <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18              0x400001c6>,    /* SODIMM 95 */
1180                         <MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19              0x400001c6>;    /* SODIMM 93 */
1181         };
1182
1183         /* Verdin I2C_1 */
1184         pinctrl_i2c4: i2c4grp {
1185                 fsl,pins =
1186                         <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL                0x400001c6>,    /* SODIMM 14 */
1187                         <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA                0x400001c6>;    /* SODIMM 12 */
1188         };
1189
1190         pinctrl_i2c4_gpio: i2c4gpiogrp {
1191                 fsl,pins =
1192                         <MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20              0x400001c6>,    /* SODIMM 14 */
1193                         <MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21              0x400001c6>;    /* SODIMM 12 */
1194         };
1195
1196         /* Verdin I2C_3_HDMI */
1197         pinctrl_i2c5: i2c5grp {
1198                 fsl,pins =
1199                         <MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL            0x400001c6>,    /* SODIMM 59 */
1200                         <MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA            0x400001c6>;    /* SODIMM 57 */
1201         };
1202
1203         pinctrl_i2c5_gpio: i2c5gpiogrp {
1204                 fsl,pins =
1205                         <MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26          0x400001c6>,    /* SODIMM 59 */
1206                         <MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27          0x400001c6>;    /* SODIMM 57 */
1207         };
1208
1209         /* Verdin I2S_2_BCLK (TOUCH_RESET#) */
1210         pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp {
1211                 fsl,pins =
1212                         <MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00              0x184>; /* SODIMM 42 */
1213         };
1214
1215         /* Verdin I2S_2_D_OUT shared with SAI3 */
1216         pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp {
1217                 fsl,pins =
1218                         <MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01              0x184>; /* SODIMM 46 */
1219         };
1220
1221         pinctrl_pcie: pciegrp {
1222                 fsl,pins =
1223                         <MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19             0x4>,   /* SODIMM 244 */
1224                         <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19           0x1c4>; /* PMIC_EN_PCIe_CLK, unused */
1225         };
1226
1227         pinctrl_pmic: pmicirqgrp {
1228                 fsl,pins =
1229                         <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03            0x1c4>; /* PMIC_INT# */
1230         };
1231
1232         pinctrl_pwm_1: pwm1grp {
1233                 fsl,pins =
1234                         <MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT           0x6>;   /* SODIMM 15 */
1235         };
1236
1237         pinctrl_pwm_2: pwm2grp {
1238                 fsl,pins =
1239                         <MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT              0x6>;   /* SODIMM 16 */
1240         };
1241
1242         /* Verdin PWM_3_DSI shared with GPIO3_IO20 */
1243         pinctrl_pwm_3: pwm3grp {
1244                 fsl,pins =
1245                         <MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT                0x6>;   /* SODIMM 19 */
1246         };
1247
1248         /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM3_OUT */
1249         pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsi1hpdgpiogrp {
1250                 fsl,pins =
1251                         <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20              0x184>; /* SODIMM 19 */
1252         };
1253
1254         pinctrl_reg_eth: regethgrp {
1255                 fsl,pins =
1256                         <MX8MP_IOMUXC_SD2_WP__GPIO2_IO20                0x184>; /* PMIC_EN_ETH */
1257         };
1258
1259         pinctrl_sai1: sai1grp {
1260                 fsl,pins =
1261                         <MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK             0x96>,  /* SODIMM 38 */
1262                         <MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00        0x1d6>, /* SODIMM 36 */
1263                         <MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK          0x1d6>, /* SODIMM 30 */
1264                         <MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC          0x1d6>, /* SODIMM 32 */
1265                         <MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00        0x96>;  /* SODIMM 34 */
1266         };
1267
1268         pinctrl_sai3: sai3grp {
1269                 fsl,pins =
1270                         <MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x1d6>, /* SODIMM 48 */
1271                         <MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK   0x1d6>, /* SODIMM 42 */
1272                         <MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x96>,  /* SODIMM 46 */
1273                         <MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC  0x1d6>; /* SODIMM 44 */
1274         };
1275
1276         pinctrl_uart1: uart1grp {
1277                 fsl,pins =
1278                         <MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS          0x1c4>, /* SODIMM 135 */
1279                         <MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS          0x1c4>, /* SODIMM 133 */
1280                         <MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX           0x1c4>, /* SODIMM 129 */
1281                         <MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX           0x1c4>; /* SODIMM 131 */
1282         };
1283
1284         pinctrl_uart2: uart2grp {
1285                 fsl,pins =
1286                         <MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS          0x1c4>, /* SODIMM 143 */
1287                         <MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS          0x1c4>, /* SODIMM 141 */
1288                         <MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX           0x1c4>, /* SODIMM 137 */
1289                         <MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX           0x1c4>; /* SODIMM 139 */
1290         };
1291
1292         pinctrl_uart3: uart3grp {
1293                 fsl,pins =
1294                         <MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX           0x1c4>, /* SODIMM 147 */
1295                         <MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX           0x1c4>; /* SODIMM 149 */
1296         };
1297
1298         /* Non-wifi usage only */
1299         pinctrl_uart4: uart4grp {
1300                 fsl,pins =
1301                         <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX           0x1c4>, /* SODIMM 151 */
1302                         <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX           0x1c4>; /* SODIMM 153 */
1303         };
1304
1305         pinctrl_usb1_vbus: usb1vbusgrp {
1306                 fsl,pins =
1307                         <MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12            0x106>; /* SODIMM 155 */
1308         };
1309
1310         /* USB_1_ID */
1311         pinctrl_usb_1_id: usb1idgrp {
1312                 fsl,pins =
1313                         <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10           0x1c4>; /* SODIMM 161 */
1314         };
1315
1316         /* USB_1_OC# */
1317         pinctrl_usb_1_oc_n: usb1ocngrp {
1318                 fsl,pins =
1319                         <MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC           0x1c4>; /* SODIMM 157 */
1320         };
1321
1322         pinctrl_usb2_vbus: usb2vbusgrp {
1323                 fsl,pins =
1324                         <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14            0x106>; /* SODIMM 185 */
1325         };
1326
1327         /* On-module Wi-Fi */
1328         pinctrl_usdhc1: usdhc1grp {
1329                 fsl,pins =
1330                         <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK               0x190>,
1331                         <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD               0x1d0>,
1332                         <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0           0x1d0>,
1333                         <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1           0x1d0>,
1334                         <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2           0x1d0>,
1335                         <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3           0x1d0>;
1336         };
1337
1338         pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
1339                 fsl,pins =
1340                         <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK               0x194>,
1341                         <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD               0x1d4>,
1342                         <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0           0x1d4>,
1343                         <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1           0x1d4>,
1344                         <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2           0x1d4>,
1345                         <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3           0x1d4>;
1346         };
1347
1348         pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1349                 fsl,pins =
1350                         <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK               0x196>,
1351                         <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD               0x1d6>,
1352                         <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0           0x1d6>,
1353                         <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1           0x1d6>,
1354                         <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2           0x1d6>,
1355                         <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3           0x1d6>;
1356         };
1357
1358         pinctrl_usdhc2_cd: usdhc2cdgrp {
1359                 fsl,pins =
1360                         <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12              0x1c4>; /* SODIMM 84 */
1361         };
1362
1363         pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp {
1364                 fsl,pins =
1365                         <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12              0x0>;   /* SODIMM 84 */
1366         };
1367
1368         pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
1369                 fsl,pins =
1370                         <MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22              0x4>;   /* SODIMM 76 */
1371         };
1372
1373         pinctrl_usdhc2: usdhc2grp {
1374                 fsl,pins =
1375                         <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT        0x4>,   /* PMIC_USDHC_VSELECT */
1376                         <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK               0x190>, /* SODIMM 78 */
1377                         <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD               0x1d0>, /* SODIMM 74 */
1378                         <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0           0x1d0>, /* SODIMM 80 */
1379                         <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1           0x1d0>, /* SODIMM 82 */
1380                         <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2           0x1d0>, /* SODIMM 70 */
1381                         <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3           0x1d0>; /* SODIMM 72 */
1382         };
1383
1384         pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
1385                 fsl,pins =
1386                         <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT        0x4>,
1387                         <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK               0x194>,
1388                         <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD               0x1d4>,
1389                         <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0           0x1d4>,
1390                         <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1           0x1d4>,
1391                         <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2           0x1d4>,
1392                         <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3           0x1d4>;
1393         };
1394
1395         pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
1396                 fsl,pins =
1397                         <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT        0x4>,
1398                         <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK               0x196>,
1399                         <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD               0x1d6>,
1400                         <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0           0x1d6>,
1401                         <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1           0x1d6>,
1402                         <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2           0x1d6>,
1403                         <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3           0x1d6>;
1404         };
1405
1406         /* Avoid backfeeding with removed card power */
1407         pinctrl_usdhc2_sleep: usdhc2slpgrp {
1408                 fsl,pins =
1409                         <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT        0x0>,
1410                         <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK               0x100>,
1411                         <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD               0x100>,
1412                         <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0           0x100>,
1413                         <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1           0x100>,
1414                         <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2           0x100>,
1415                         <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3           0x100>;
1416         };
1417
1418         pinctrl_usdhc3: usdhc3grp {
1419                 fsl,pins =
1420                         <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B        0x1d1>,
1421                         <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE         0x190>,
1422                         <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5          0x1d0>,
1423                         <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6          0x1d0>,
1424                         <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7            0x1d0>,
1425                         <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0         0x1d0>,
1426                         <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1         0x1d0>,
1427                         <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2         0x1d0>,
1428                         <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3         0x1d0>,
1429                         <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4           0x1d0>,
1430                         <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK             0x190>,
1431                         <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD             0x1d0>;
1432         };
1433
1434         pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1435                 fsl,pins =
1436                         <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B        0x1d1>,
1437                         <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE         0x194>,
1438                         <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5          0x1d4>,
1439                         <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6          0x1d4>,
1440                         <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7            0x1d4>,
1441                         <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0         0x1d4>,
1442                         <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1         0x1d4>,
1443                         <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2         0x1d4>,
1444                         <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3         0x1d4>,
1445                         <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4           0x1d4>,
1446                         <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK             0x194>,
1447                         <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD             0x1d4>;
1448         };
1449
1450         pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1451                 fsl,pins =
1452                         <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B        0x1d1>,
1453                         <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE         0x196>,
1454                         <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5          0x1d2>,
1455                         <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6          0x1d2>,
1456                         <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7            0x1d2>,
1457                         <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0         0x1d2>,
1458                         <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1         0x1d2>,
1459                         <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2         0x1d2>,
1460                         <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3         0x1d2>,
1461                         <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4           0x1d2>,
1462                         <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK             0x196>,
1463                         <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD             0x1d6>;
1464         };
1465
1466         pinctrl_wdog: wdoggrp {
1467                 fsl,pins =
1468                         <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B          0xc6>;  /* PMIC_WDI */
1469         };
1470
1471         pinctrl_bluetooth_ctrl: bluetoothctrlgrp {
1472                 fsl,pins =
1473                         <MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08             0x1c4>; /* WIFI_WKUP_BT */
1474         };
1475
1476         pinctrl_wifi_ctrl: wifictrlgrp {
1477                 fsl,pins =
1478                         <MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09             0x1c4>; /* WIFI_WKUP_WLAN */
1479         };
1480
1481         pinctrl_wifi_i2s: wifii2sgrp {
1482                 fsl,pins =
1483                         <MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21             0x1d6>, /* WIFI_TX_SYNC */
1484                         <MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21             0x96>,  /* WIFI_RX_DATA0 */
1485                         <MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23             0x1d6>, /* WIFI_TX_BCLK */
1486                         <MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24             0x1d6>; /* WIFI_TX_DATA0 */
1487         };
1488
1489         pinctrl_wifi_pwr_en: wifipwrengrp {
1490                 fsl,pins =
1491                         <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11            0x184>; /* PMIC_EN_WIFI */
1492         };
1493 };